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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. features ? aal1 segmentation and reassembly device capable of simultaneously processing up to 2048 bidirectional vcs ? aal1 cell format for "structured ds1/e1 n x 64kbps service" as per atm forum af-vtoa- 0078.000 "circuit emulation services interoperability specifications" (nx64 basic service, ds1 nx64 service with cas, and e1 nx64 service with cas) ? two utopia ports (level 2, 16-bit, 50 mhz) with loopback function for dual fibre ring applications ? third utopia port for connection to an external aal5 sar processor, or for chaining multiple mt90503 or other sar or ima devices ? flexible aggregation capabilities (nx64) to allow any combination of 64 kbps ? tdm bus provides 32 bidirectional serial tdm streams at 2.048, 4.096, or 8.192 mbps for up to 4096 tdm 64 kbps channels ? compatible with h.100 and h.110 interfaces ? tdm to atm transmission latency less than 250 s ? support for clock recovery - adaptive clock recovery, synchronous residual time stamp (srts) or external ? support master and slave tdm bus clock operation ? 8- or 16-bit microprocessor port, configurable to motorola or intel timing ? master clock rate up to 80 mhz ? single power supply device (3.3v) ? ieee 1149 (jtag) interface december 2004 ordering information MT90503AG 503 pin pbga for temperature range, see page 207. mt90503 2048vc aal1 sar data sheet figure 1 - functionl block diagram tdm module clock recovery submodule data memory controller data memory (external ssram) cpu module registers control memory controller control memory (external ssram) rx_sar module tx_sar module utopia module port a port b port c boundary scan logic address bus and 8- or 16-bit data bus rxa port txa port rxb port txb port rxc port txc port jtag interface clock signals h.100/ h.110 tdm bus 4096 x 64kbps
mt90503 data sheet 2 zarlink semiconductor inc. description the mt90503 is an aal1 sar, which offers a highly integrated solution for interfacing telecom bus-based systems with atm networks. the device has the capability of simu ltaneously processing 2048 bidirectional channels of 64 kbps. the mt90503 can be connected directly to an h.100 or h.110 compatible bus. the device also offers the capability of using channel associated signalling (cas) to support circuit emulation service (ces) for structured data transfer (sdt). the interface to the tdm port is provided by a tdm bus, wh ich consists of 32 bidirect ional serial tdm data streams at 2.048, 4.096, or 8.192 mbps, ther efore allowing for 2048 bidirectional tdm channels operating at 64 kbps. this tdm bus is compatible with the ectf h.100 and h.110 specifications. the interface to the atm domain is provided by three utop ia ports (ports a, b, and c). all three of the utopia ports can operate in atm (master) or phy (slave) mode. port a can also be configured as level 2 m-phy mode. applications ? atm access and multiplexing equipment ? switching platforms that provide internetworking between tdm and atm ? atm edge switches ? atm uplink for expansion of cos, pbxs, or open switching platforms using an adjunct atm switch ? integrated digital loop carrier (idlc) ? sonet or sdh add and drop multiplexers (adm) ? next generation digital loup carrier (ngdic) ? digital subscriber line access multiplexer dslam with gateway switching feature ? cells coming in from any of the utopia ports can be switched to any other port. the user has the option to change the vpi and vci fields. purchase of this product does not grant the purchaser any rights under patent no. 5,260,978. use of this product or its re-sale as a component of another product may require a license under the patent which is available from telcordia technologies, inc., 445 south street , morristown, new jersey 07960. zarlink assumes no responsibility or liability that may result from its customers' use of zarlink products with respect to this patent. in particular, zarlink's patent indemnity in its terms and conditions of sales which are set out in its sales acknowledgements and invoices does not apply to this patent.
mt90503 data sheet 3 zarlink semiconductor inc. figure 2 - atm switch application 2048 aali sar mt90503 28 port aal1 sar mt90528 octal/ima mt90220 atm utopia bus octal t1/e1 framers mt9072 m13 mux t3/e3 liu clock digital pll oscillator mt9045 clock digital pll oscillator mt9045 stratum 3 timing card stratum 3 timing card t1/e1 liu t1/e1 framers t1/e1 ima uplink oc-12 framers & atm cell access optical interface & drivers traffic management & switching atm network uplink mt9076 t1/e1 circuit emulation services t3/e3 pstn sdt pstn udt traffic atm traffic traffic channels
mt90503 data sheet table of contents 4 zarlink semiconductor inc. 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1 functional overview of the mt90503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.0 features detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 tdm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 atm sar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 particular modes of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.0 pin designations and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.1 cpu interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.1.1 example interrupt flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.1.2 interrupt initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.1.3 interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.2 intel/motorola interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1.2.1 extended indirect accessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.2 extended indirect writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.3 extended indirect reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.4 extended direct accessing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.2.5 extended direct writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.2.6 extended direct reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.3 mt90503 reset procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 tdm module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.1 tdm bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.2 tdm bus clocking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.3 tdm datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.4 tdm channel association structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.4.1 non cas operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.4.2 cas operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.5 tdm circular buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.6 tdm circular buffer pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.6.1 non-multiframing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.6.2 e1/t1 multiframing (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3 tx_sar module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.1.1 support and trunking for different types of atm cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.2 tx_sar event schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.2 the transmit event scheduler process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.3 transmit event scheduler fields description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.2.4 scheduler events fields description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.3.2.5 bandwidth limitations for transmit scheduler events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.3 out of bandwidth error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.3.1 percent of bandwidth register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.3.2 distribution of events by software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.4 mapping of the transmit event scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.5 tx_sar control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.5.1 tx_sar control structure fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
mt90503 data sheet table of contents 5 zarlink semiconductor inc. 4.3.6 miscellaneous tx_sar features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.6.1 t1 with cas and e1 with cas cell format mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.6.2 support of partially-filled cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.6.3 tx_sar fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4 rx_sar module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4.1 treatment of data cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4.2 control structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4.3 errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.4 error report structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5 utopia module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.2 utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.3 errors on received cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5.4 transmit and receive state machines for atm and phy mo des . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.5 cell router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.6 match & mask for cell routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.6.1 look-up tables entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.6.2 lut addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.6.3 utopia clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5.7 led operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5.8 utopia flow control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.5.9 external interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.6 clock recovery module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1.1 two point generation modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1.2 one srts (synchronous residual time stamp) generating module. . . . . . . . . . . . . . . . . . . . 87 4.6.1.3 three integer divisor clock modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.6.1.4 two precise clock modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.1.5 eleven multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.2 multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.3 integer divisor clocks (idclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.6.4 precise clocks (pclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.6.5 point generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.6.6 adaptive clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.6.6.1 srts clock recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.7 srts transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.6.8 external memory point format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.0 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.1 memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3 memory controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.1 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.2 control memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.3 data memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.4 control memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.4 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.5 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.2 main registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.5.3 utopia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.5.4 tdm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.5.5 tx_sar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
mt90503 data sheet table of contents 6 zarlink semiconductor inc. 5.5.6 scheduler registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.5.7 rx_sar registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.5.8 clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.5.9 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.5.10 h.100 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.0 statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.1 tdm statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.2 tx sar statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3 rx sar statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.4 utopia statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.0 programming the fast_clk pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 8.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 8.1 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 8.1.1 precautions during power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.1.2 precautions during power failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.1.3 pull-ups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.2 h.110 diode clamp rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.3 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 9.0 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 9.1 cpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 9.2 utopia interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 9.3 external memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9.4 h.100/h.110 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 9.5 h.100/h.110 clocking signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 10.0 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
mt90503 data sheet list of figures 7 zarlink semiconductor inc. figure 1 - functionl block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - atm switch application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3 - transmit data flow - tdm to utopia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4 - receive data flow - utopia to tdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5 - pll pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6 - tdm serial to parallel/parallel to serial (spps) conv erter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 7 - cas and mfs transport on the tdm bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 8 - tdm data path controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9 - tdm channel association structur es: tx channel non-cas mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 10 - tdm channel association: rx channels (non cas mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 11 - tdm channel association: tx channels (cas mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 12 - tdm channel association: rx channels (cas mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 13 - cas change structure in control memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 14 - tx/rx circular buffer and size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 15 - silent pattern buffer a/b in control memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 16 - tdm circular buffer (one multiframe in t1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 17 - tdm circular buffer (one super frame in e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 18 - tdm circular buffers (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 19 - tdm circular buffer (complete buffer in e1 mode, strict multiframing) . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20 - tdm circular buffer (complete buffer in e1 mode, fastcas) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 21 - tdm circular buffer (complete buffer in t1 mode, strict multiframing) . . . . . . . . . . . . . . . . . . . . . . . 55 figure 22 - tdm circular buffer (complete buffer in t1 mode, fastcas) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 23 - atm cell formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 24 - transmit event scheduler process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 25 - unsyncrhonised schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 26 - synchronised schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 27 - partially synchronised schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 28 - tx_sar event scheduler pointer flow and control structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 29 - tx_sar control structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 30 - rx_sar control structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 31 - overrun and underrun examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 32 - rx_sar error report structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 33 - utopia module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 34 - atm mode state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 35 - phy mode state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 36 - cell format for cells in internal utopia input and output cell fifos . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 37 - cell router flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 38 - match & mask example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 39 - short and long look-up table entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 40 - vpi/vci concatenation and lut entry address example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 41 - utopia clock generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 42 - external utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 43 - multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 44 - integer clock processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 45 - adaptive clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 46 - adaptive cell reception flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 47 - rx srts clock recovery module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 48 - tx srts clock recovery module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
mt90503 data sheet list of figures 8 zarlink semiconductor inc. figure 49 - clock recovery information buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 50 - mem_clk output and fast_clk generation circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 51 - mem_clk input and mclk generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 52 - non-multiplexed cpu write access - intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 53 - non-multiplexed cpu read access - intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 54 - multiplexed cpu write access - intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 55 - multiplexed cpu read access - intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 56 - non-multiplexed cpu interface write access - motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 57 - non-multiplexed cpu interface read access - motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 15 figure 58 - multiplexed cpu interface write access - motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 59 - multiplexed cpu interface read access - motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 60 - utopia timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 61 - flowthrough zbt external memory timing - write acce ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 62 - flowthrough zbt external memory timing - read acce ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 63 - flowthrough ssram external memory timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1 figure 64 - flowthrough ssram external memory timing - read ac cess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 65 - late-write external memory timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 66 - late-write external memory timing - read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 67 - pipelined zbt external memory timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 68 - pipelined zbt external memory timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 69 - pipelined external memory timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 figure 70 - pipelined external memory timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 figure 71 - h.100 input, output, and frame sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 72 - h.100 message channel clock, transmission delay, and reception delay. . . . . . . . . . . . . . . . . . . 226 figure 73 - h.100 clock skew (when chip is master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 74 - h.100/h.110 clocking signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 75 - tdm bus timing - compatibility clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 76 - tdm data bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
mt90503 data sheet list of tables 9 zarlink semiconductor inc. table 1 - cpu bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 2 - control memory bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3 - data memory bus interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4 - data and control memory clock pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5 - h.100/h.110 bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 6 - clock recovery pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7 - test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8 - utopia interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9 - phase lock loop (pll) pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10 - process monitor pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11 - pin names listed by location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12 - pinout summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13 - cpu interface mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 14 - control register (0000h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15 - read/write data register (0004h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16 - address high register (0008h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17 - address low register (000ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18 - field description for the transmit event scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 19 - scheduler event fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 20 - maximum number of events per frame for common transmission speeds . . . . . . . . . . . . . . . . . . . . 61 table 21 - examples of typical transmit event scheduler sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 22 - description of the fields for the tx_sar control stru cture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 23 - description of the fields for the rx_sar structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 24 - payload sizes for various cell formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 25 - rx_sar errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 26 - description of the fields for the rx_sar error report structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 27 - multiplexer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 28 - source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 29 - idclk_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 30 - pclk registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 31 - adapsrts0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 32 - tx srts registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 33 - srts pointer buffer, field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 34 - mt90503 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 35 - types of data memory accesses for each agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 36 - types of control memory accesses for each agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 37 - cpu control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 38 - cpu status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 39 - cpu interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 40 - cpu counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 41 - led1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 42 - led2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 43 - pll configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 44 - intel/motorola address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 45 - intel/motorola address rise register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 46 - intel/motorla address fall register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 47 - intel/motorola data out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 48 - intel/motorola data in register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
mt90503 data sheet list of tables 10 zarlink semiconductor inc. table 49 - intel/motorola data rise/fall register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 50 - main control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 51 - main status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 52 - main interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 53 - main counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 54 - interrupt flags register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 55 - interrupt1 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 56 - interrupt2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 57 - interrupt1 enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 58 - interrupt2 enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 59 - utopia clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 60 - utopia clock generation a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 61 - utopia clock generation b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 62 - utopia clock generation c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 63 - control memory parity0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 64 - control memory parity1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 65 - control memory configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 66 - data memory parity 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 67 - data memory parity 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 68 - data memory configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 69 - utopia control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 70 - utopia control1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 71 - utopia status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 72 - utopia status 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 73 - utopia interrupt enable 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 74 - utopia counters register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 75 - cell loss counters register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 76 - port a look up table address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 77 - port a vpi/vci identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 78 - port a concatenation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 79 - port a vpi match register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 80 - port a vci mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 81 - port a vci match register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 82 - port a vci mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 83 - port a cell arrival counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 84 - port a cell arrival counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 85 - port a cell departure counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 86 - port a cell departure low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 87 - port a overflow0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 88 - port a overflow1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 89 - port a address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 90 - port b look up table register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 91 - port b vpi/vci identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 92 - port b concatenation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 93 - port b vpi match register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 94 - port b vpi mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 95 - port b vci match register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 97 - port b cell arrival counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
mt90503 data sheet list of tables 11 zarlink semiconductor inc. table 98 - port b cell arrival counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 99 - port b cell departure counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 96 - port b vci mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 100 - port b cell departure counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 101 - port b overflow0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 102 - port b overflow1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 103 - port c look up table register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 104 - port c vpi/vci identification register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 105 - port c concatenation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 106 - port c vpi match register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 107 - port c vpi mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 108 - port c vci match register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 109 - port c vci match register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 110 - port c cell arrival counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 111 - port c cell arrival counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 112 - port c cell departure counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 113 - port c cell departure counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 114 - port c overflow0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 115 - port c overflow1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 116 - tx_sar cell arrival counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 117 - tx_sar cell arrival counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 118 - rx_sar cell departure counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 119 - rx_sar cell departure counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 120 - tx_sar overflow0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 121 - tx_sar overflow1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 122 - hec byte control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 123 - unknown header routing register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 124 - unknown oam routing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 125 - gpio input0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 126 - gpio input1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 127 - gpio input2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 128 - txa data status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 129 - txa data interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 130 - rxa data status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 131 - rxa data interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 132 - txb data status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 133 - txb data interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 134 - rxb data status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 135 - rxb data interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 136 - gpio status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 137 - gpio status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 138 - gpio output0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 139 - gpio output1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 140 - gpio output2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 141 - gpio output enable0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 142 - gpio output enable1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 143 - gpio output enable2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 144 - tdm control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
mt90503 data sheet list of tables 12 zarlink semiconductor inc. table 145 - tdm status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 146 - cut vc tsst register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 147 - tsst underrun register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 148 - tsst cas underrun register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 149 - tdm interrupt 0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 150 - tdm interrupt 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 151 - tdm interrupt enable misc. register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 152 - tdm write pointer 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 153 - tdm write pointer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 154 - tdm read pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 155 - tx_sar control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 156 - tx_sar status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 157 - tx_sar interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 158 - tx_sar control 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 159 - tx_sar data read pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 160 - tx_sar data write pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 161 - tx_sar data address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 162 - tx_sar data cell size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 163 - percent of bandwidth register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 164 - scheduler test status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 165 - scheduler status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 166 - scheduler interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 167 - frame latency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 168 - scheduler configuration & enable 0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 169 - scheduler configuration & enable 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 170 - scheduler configuration & enable 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 171 - scheduler configuration & enable 3 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 172 - rx_sar control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 173 - rx_sar status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 174 - rx_sar interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 175 - rx_sar data read pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 176 - rx_sar data write pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 177 - rx_sar data address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 178 - rx_sar data cell size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 179 - error structure read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 180 - error structure write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 181 - error structure address high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 182 - error structure address low register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 183 - error structure size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 184 - aal0 timeout high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 185 - aal0 timeout low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 186 - error timeout high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 187 - error timeout low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 188 - treated pulses register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 189 - clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 190 - clock status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 191 - status interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 192 - mclk alarm 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
mt90503 data sheet list of tables 13 zarlink semiconductor inc. table 193 - mclk counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 194 - mclk counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 195 - mclk alarm 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 196 - mclk alarm 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 197 - tx_srts 0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 198 - tx_srts 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 199 - tx_srts 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 200 - tx_srts 4 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 201 - tx_srts 5 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 202 - adaptive srts0 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 203 - adaptive srts0 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 204 - adaptive srts0 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 205 - adaptive srts0 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 206 - adaptive srts0 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 207 - adaptive srts0 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 208 - adaptive srts0 6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 209 - adaptive srts0 7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 210 - adaptive srts0 8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 211 - adaptive srts0 9 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 212 - adaptive srts1 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 213 - adaptive srts1 1register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 214 - adaptive srts1 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 215 - adaptive srts1 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 216 - adaptive srts1 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 217 - adaptive srts1 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 218 - adaptive srts1 6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 219 - adaptive srts1 7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 220 - adaptive srts1 8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 221 - adaptive srts1 9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 222 - pin mux 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 223 - pin mux 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 224 - pin mux 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 225 - pin mux 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 226 - pin mux 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 227 - pin mux 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 228 - integer clock divisor0 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 229 - integer clock divisor0 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 230 - integer clock divisor0 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 231 - integer clock divisor0 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 232 - integer clock divisor0 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 233 - integer clock divisor0 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 234 - integer clock divisor0 8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 235 - integer clock divisor0 9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 236 - integer clock divisor0 10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 237 - integer clock divisor1 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 238 - integer clock divisor1 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 239 - integer clock divisor1 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 240 - integer clock divisor1 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
mt90503 data sheet list of tables 14 zarlink semiconductor inc. table 241 - integer clock divisor1 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 242 - integer clock divisor1 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 243 - integer clock divisor1 8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 244 - integer clock divisor1 9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 245 - integer clock divisor1 10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 246 - integer clock divisor2 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 247 - integer clock divisor2 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 248 - integer clock divisor2 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 249 - integer clock divisor2 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 250 - integer clock divisor2 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 251 - integer clock divisor2 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 252 - integer clock divisor2 8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 253 - integer clock divisor2 9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 254 - integer clock divisor2 10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 255 - tx srts debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 256 - rx srts debug 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 257 - rx srts debug 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 258 - aal1 error debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 259 - miscellaneous control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 260 - miscellaneous error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 261 - silent tone 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 262 - silent tone 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 263 - silent tone 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 264 - adaptive point/srts value 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 265 - adaptive point/srts base address low 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 266 - adaptive point/srts base address high 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 267 - adaptive point/srts write pointer 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 268 - adaptive point/srts read pointer 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 269 - local srts write pointer 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 270 - local srts read pointer 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 271 - adaptive point/srts value 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 272 - adaptive point/srts base address low 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 273 - adaptive point/srts base address high 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 274 - adaptive point/srts write pointer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 275 - adaptive point/srts read pointer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 276 - local srts write pointer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 277 - local srts read pointer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 278 - cas change buffer size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 279 - cas change buffer base address low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 280 - cas change buffer base address high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 281 - cas write pointer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 282 - cas read pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 283 - cas timeout high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 284 - cas timeout low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 285 - treated pulses register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 286 - h.100 control 0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 287 - h.100 control 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 288 - h.100 control 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
mt90503 data sheet list of tables 15 zarlink semiconductor inc. table 289 - h.100 flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 290 - h.100 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 291 - h.100 interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 292 - register 0128h frequency values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 293 - z divisor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 294 - clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 295 - mclk - master clock input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 296 - non-multiplexed cpu interface intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 297 - multiplexed cpu interface intel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 298 - non-multiplexed cpu interface motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 299 - multiplexed cpu interface motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 300 - t5 read access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 301 - utopia bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 302 - memory interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 303 - h.100/h.110 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 304 - h.100/h.110 clocking signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
mt90503 data sheet 16 zarlink semiconductor inc. 1.0 introduction 1.1 functional overview of the mt90503 the mt90503 is an aal1 sar, which offers a highly integrated solution for interfacing telecom bus-based systems with atm networks. the device has the capability of simu ltaneously processing 2048 bi-directional channels of 64 kbps. the mt90503 can be connected directly to an h.100 or h.110 compatible bus. the device also offers the capability of using channel associated signalling (cas) to support circuit emulation service (ces) for structured data transfer (sdt). the interface to the tdm port is provided by a tdm bu s, which consists of 32 bi -directional serial tdm data streams at 2.048, 4.096, or 8.192 mbps , therefore allowing for 2048 bi-dir ectional tdm channels operating at 64 kbps. this tdm bus is compatible with the ectf h.100 and h.110 specifications. the interface to the atm domain is provided by three utop ia ports (ports a, b, and c). all three of the utopia ports can operate in atm (master) or phy (slave) mode. port a is a utopia level 2 interface which can operate at up to 50 mhz using a 16- or an 8-bit data bus. this port is capable of operating in atm-mode (single-phy), in ph y-mode (slave-mode or level 1), or in slave mphy-mode (level 2). port b is a utopia level 2 interface, which can operate at up to 50 mhz using a 16- or an 8-bit data bus but does not support bus addressing. this po rt is capable of operating in at m-mode (single-phy), in phy-mode (slave-mode). port c is a utopia level 1 interface which can operate at up to 50 mhz using an 8-bit data bus. this port is capable of operating in atm-mode (master-mode), or in phy-mode (slave-mode). the mt90503 is capable of performing a utopia loopback from any incoming utopia port to any outgoing utopia port, including a loopback to the port of origin. the lo opback capability could be used fo r dual fibre ri ng applications. figure 3 shows the data flow from the h.1 00/h.110 bus to the tx utopia interface. figure 3 - transmit data flow - tdm to utopia h.100/h.110 bus tdm bus tx sar internal memory tx utopia interface utopia output utopia cell router utopia input fifo circular buffers[15:8] (external data memory) path controlled by tdm module path controlled by tx sar module path controlled by utopia module time-slot memories
mt90503 data sheet 17 zarlink semiconductor inc. figure 4 shows the dataflow from the rx utopa interface to the h.100/h.110 bus. figure 4 - receive data flow - utopia to tdm 2.0 features detailed description 2.1 utopia interface ? contains 3 utopia ports with transmit and receive interfaces: - port a: 16-bit or 8-bit utopia level 2, atm mode (sin gle-phy) or phy mode (single or multi-phy). accepts data rates up to 622 mb/s. - port b: 16-bit or 8-bit utopia lev el 2 without bus addressing, atm m ode or phy mode (restricted to 8-bit when port a is in multi-phy mode). accepts data rates up to 622 mb/s. - port c: 8-bit utopia, atm mode or phy mode ? supports cell switching through daisy chained sar/phy devices via the utopia interface (aal5 sars, aal1 sars such as mt90503, and aal2 sars such as mt90502). ? supports both uni and nni header formats ? supports any combination of vci/vpi concaten ation up to 16 bits in atm receive direction ? supports up to 65536 virtual circuits per utopia port in atm receive direction ? rapid timing reference cell processing in receive/segmentation direction ? can eliminate null cells (vpi = 0, vci = 0) received at utopia a, b, and c port inputs ? filters received cells before accessing vcc look up table (lut) ? utopia vcc loopback for bi-directional ring functiona lity (from rx a to tx b and from rx b to tx a) ? per-vcc user cell and oam cell destination control (for vcs that have a lut entry) ? per-utopia-port user cell and oam cell destination control (for vcs that do not have a lut entry) h.100/h.110 bus tdm bus utopia input fifo utopia cell router rx utopia interface time-slot memories rx sar cbr portion utopia output fifo path controlled by tdm module path controlled by rx sar module path controlled by utopia module circular buffers[7:0] (external data memory) cpu module external control memory rx sar non-cbr portion cpu
mt90503 data sheet 18 zarlink semiconductor inc. 2.2 tdm interface ? h.100/h.110 compatible ? low latency tdm bus to tdm bus loopback of up to 2048 channels ? programmable value for the null-octet inserted during an underrun situation ? receive buffer replay capability or silent pattern insertion for underrun situations ? support of cas and mfs for ds1(esf) and e1 ? automatic detection of a change in the cas value, for cas received in atm cells, and cas received from tdm bus 2.3 clock recovery ? srts clock recovery: - dual reference vcs (for redundancy) - broadcast srts vcs in transmit /segmentation direction ? adaptive clock recovery - dual reference vcs (for redundancy) - limited jitter, precision enhanced, mc lk (chip clock) to 8 khz dividers ? direct 8 khz clock recovery: - can generate an 8 khz reference using one of 8 multipurpose timing reference pins - supports all n * 8 khz input reference, (1.544 mhz, 2.048 mhz, 19.44 mhz, etc.) up to 12500 * 8 khz - output high time and low time of the 8 khz refer ence output can be modified relative to input signal - the eight multipurpose timing reference pins can be used to support many possible clock recovery configurations, including t he following reference signals: sec8k (m vip), atm8k (to/from phy25 or from phy155), fnxi (srts), ct_netref (for ct-bus) ? can generate a 20 mhz clock for an external p ll, e.g. mt9042 or mt9044 (output on one of the multipurpose timing reference pins) 2.4 atm sar ? supports aal1 (with pointer, or without pointer byte), cbr-aal0, and cbr-aal5 (aal5-vtoa) cell formats ? supports partially filled cells, with fills from 4 to 47 bytes ? aal1 cell format for ?structured ds1/e1 nx64 kbit/s service? as per atm forum af-vtoa-0078.000 ?circuit emulation services interope rability specification? (nx64 basic service, ds1 nx64 service with cas, and e1 nx64 service with cas) ? vcs carrying 1 to 2048 tdm channels ? tdm to atm transmission latency less than 250 s (when minimum voice latency desired, and strict multiframe alignment of voice with cas not required) ? tdm to atm transmission latency less than 3.25 ms (when strict multiframe alignment of voice with cas required) ? atm to tdm reception latency less than cdv + 250 s (when minimum voice latency desired, and strict multiframe alignment of voice with cas not required) ? atm to tdm reception latency less than cdv + 6.250 ms (when strict multiframe alignment of voice with cas required) ? per vcc monitoring (receive/reassembly direction):
mt90503 data sheet 19 zarlink semiconductor inc. - cdv monitoring and delay correction fields - single cell loss, multiple cell loss , cell misinsertion, aal1 parity, aal1-crc, p-byte parity, p-byte out-of-range error bits - cell arrival counter - underrun slip counter - overrun slip counter ? per vcc monitoring (transmit/segmentation direction): - cell transmission counter ? single received cell loss compensated, replac ing the payload with a programmable null-octet ? support segmentation and reassembly of 2048 full duplex tdm channels (2048 without cas, subtract one tdm channel for each cas channel carried) ? support of up to 61 ms of cdv in non-multiframing mode, 45 ms in t1 with strict multiframing, 29 ms in e1 with strict multiframing ? aal0 cell generation / reception for software implemen ted sar function (cell buffer can contain up to 1024 cells) ? percentage of bandwidth usage register (transmit/segmentation direction) 2.5 required external components ? 128k/256k/512k x 18 control memory (can be used in up to 2 banks) ? maximum addressable control memory: 1 mb ? 128k/256k/512k x 18 data memory (can be used in up to 4 banks) ? maximum addressable data memory: 4 mb ? 8 khz to 16/mhz pll when h.100/h.110 interface used as master mode ? clock driver for mclk_src 2.6 particular modes of operation ? test modes - tx sar to rx sar internal loop-back of some vcs, while mt90503 is running - tdm bus loop-back 2.7 miscellaneous ? motorola/intel cpu interface (paged memory accesses) ? programmable maximum number of interrupts per second ? multipurpose i/os ? led pin generation for utopia interface ? parity bits on memory and utopia interfaces to ensure clocking and memory access integrity ? cpu-based oam cell treatment ? jtag (ieee 1149) test access port ? mclk speed of 80 mhz ? global reset pin with i/o tri-state
mt90503 data sheet 20 zarlink semiconductor inc. ? global power-down and tri-state 2.8 power ? 3.3v core and i/o supply ? all i/os are 3.3v with 5 v tolerance ? tdm pins are pci 5v signalling tolerant (when pci clamp rail tied to 5 v) 3.0 pin designations and descriptions the following tables identify each pin of the mt90503 device's main functional areas. a description of each pin is also provided. notes : gnd pins: a2, a4, a7, a8, a9, a12, a15, a18, a21, a22, a23, a25, a26, a28, b1, b29, d1, d26, d29, e1, e6, e29, g1, g29, h1, h29, j1, j29, l11, l13, l15, l17, l19, m1, m29, n11, n13, n15, n17, n19, r1, r11, r13, r17, r19, r29, t29, u11, u13, u15, u17, u19, v1, w11, w13, w15, w17, w19, aa1, aa29, ab1, ab29, ac1, ad5, ad25, ae1, ae13, ae29, af1, af29, ag29, ah1, ah2, ah28, aj2, aj4, aj7, aj8, aj 9, aj12, aj15, aj18, aj21, aj22, aj23, aj25, aj26, aj28 vdd 3.3v pins : a3, a5, a10, a11, a14, a16, a19, a20, a27, a29, b2, c1, c29, k1, k29, l1, l29, p1, p29, t1, v29, w1, w29, y1, y29, ac29, ag1, ah3, ah29, aj1, aj3, aj5, aj10, aj11, aj14, aj16, aj19, aj20, aj27, aj29 pins not connected: a13, b3, b4, b7, b8, b9, b12, b13, b14, b15, b16, c3, c4, c7, c8, c9, c12, c13, c14, c15, d6, d7, d8, d9, d12, d13, d14, d15, d24, e5, e8, e9, e 12, e13, e14, e15, e25, m5 , m28, t25, w25, ab25, ae4, ae5, ae22, ae23, ae25, af2, af23 1 all outputs are +3.3 v dc. 2 all input and output pins that are designated (f) can withstand 5 v dc being applied to them. 3 all input and output pins that are designated (f) are tested with a 50 pf load unless otherwise specified. 4 designations under the "rst" (reset condition) table column are: x = undefined; z = high impedance; 1 = high (+3.3 v dc ). 5 i/o types include: output (o), input (i), bi directional (i/o), powe r (pwr) and ground (gnd). 6 all buses have pins listed in order from msb to lsb.
mt90503 data sheet 21 zarlink semiconductor inc. pin rst name i/o type description ae18, af18, ag18, ah18, ae19, af19, ag19, ah19, af20, ag20, ah20, ae21, af21, ag21, ah21 z inmo_a [14:0] i ttl (f) intel/motorola interface address bus. can be used as a gpi. ae14, af14, ag14, ah14, ag15, ah15, ae16, af16 z inmo_d [7:0] i/o ttl, 4 ma (f) intel/motorola interface data bus, low bits ae12, af12, ag12, ah12, af13, ag13, ah13,aj13 z inmo_d[15:8] i/o ttl, 4 ma (f) intel/motorola interface data bus, high bits. can be used as a gpio if an 8 bit cpu interface is used. af11 mclk_src i ttl (f) master clock source . an external clock that is multiplied to generate fast_clk. ae11 reset i schmitt (f) general reset aj17 z inmo_a_das i ttl, 4 ma (f) direct access select. '1' selects the direct access space. '0' selects the indirection registers contained in the cpu interface. this pin can be connected to a[15] of an address bus but does not behave as an address pin. ah17 z inmo_cs i ttl, 4 ma (f) intel/motorola interface chip select ag17 inmo_ale i ttl (f) intel/motorola interface address latch enable af17 inmo_wr _r/w i ttl (f) intel write or motorola read/write ah16 inmo_rd_ds i ttl (f) intel read or motorola data strobe ag16 z inmo_rdy_ndtack o ttl, 8 ma (f) intel/motorola interface ready/data acknowledge. this pin is active high for intel (rdy) and active low for motorola (ndtack). ae20 cpu_mode[0] i ttl (f) cpu interf ace mode select bit 0. the cpu interface mode select bits must be hardwired. ag22 cpu_mode[1] i ttl (f) cpu interface mode select bit 1. ah22 cpu_mode[2] i ttl (f) cpu interface mode select bit 2. af22 cpu_mode[3] i ttl (f) cpu interface mode select bit 3. ah11 z interrupt1 o 4 ma (f) frequency-controllable global interrupt ag11 z interrupt2 o 4 ma (f) instant global interrupt table 1 - cpu bus interface pins
mt90503 data sheet 22 zarlink semiconductor inc. pin rst name i/o type description ag23, ah23, ae24, af24, ag24, ah24, aj24, af25, ag25, ah25, ag26, ah26, ah27, aa26, aa27, aa28, w27, w28 x cmem_a [17:0] o 4 ma control memory address bus w26 1 1. cmem_a [18] 2. cmem_cs [1] 1. o 2. o 4 ma 1. control memory address bus 2. control memory chip select 1. ag28, af27, ae26, ae28, ad27, ac26, ac28, ab27, af28, ae27, ad26, ac25, ac27, ab26, ab28, aa25 z cmem_d[15:0] i/o ttl, 4 ma control memory data bus. y25 1 cmem_cs [0] o 4 ma control memo ry chip select 0 y27 x cmem_bws [0] o 4 ma control memory byte write select 0. y26 x cmem_bws [1] o 4 ma control memory byte write select 1. y28 x cmem_r/w o 4 ma control memory r/w. this signal is only used for late write memories. ag27, af26 z cmem_par[1:0] i/o ttl, 4 ma control memory parity 1:0 table 2 - control memory bus interface pins
mt90503 data sheet 23 zarlink semiconductor inc. pin rst name i/o type description t28, k26, v28, u29, t27, t26, r28, k25, j27, j26, h28, h27, l25, h25, j28, g27, f25, f27, f29 x dmem_a[18:0] o 4 ma data memory address bus p25, n28, n26, m27, l28, l26, k28, k27, p28, p26, n29, n27, n25, m26, l27, m25 z dmem_d[15:0] i/o ttl, 4 ma data memory data bus u25 xdmem_r/w o 4 ma data memory r/w. this signal is only used for late write memories. u26 xdmem_bws [0] o 4 ma data memory byte write select 0. u27 xdmem_bws [1] o 4 ma data memory byte write select 1. u28 1dmem_cs [0] o 4 ma data memory chip select 0 v27 1dmem_cs [1] o 4 ma data memory chip select 1 v26 1dmem_cs [2] o 4 ma data memory chip select 2 v25 1dmem_cs[ 3] o 4 ma data memory chip select 3 r27 z dmem_par[0] i/o ttl, 4 ma data memory parity 0 p27 z dmem_par[1] i/o ttl, 4 ma data memory parity 1 table 3 - data memory bus interface pins pin rst name i/o type description ad29 mem_clk_i i ttl data and control memory clocks ad28 x mem_clk_o o 4 ma data and control memory clocks r26 mem_clk_positive_i i pecl data and control memory clocks, pecl r25 mem_clk_negative_i i pecl data and control memory clocks, pecl af15 x mem_clk_positive_o o pecl data and control memory clocks, pecl ae15 x mem_clk_negative_o o pecl data and control memory clocks, pecl table 4 - data and control memory clock pins
mt90503 data sheet 24 zarlink semiconductor inc. pin rst name i/o type description b17, a17, e22, d17, b19, b18, e16, c18, c16, c20, e18, e17, d16, e21, b22, b21, b20, b23, e19, c19, d23, d22, c22, d19, c24, b24, a24, e20, c21, b26, c23, d21 z ct_d[31:0] i/o pci (f) h.100/h.110 serial data bus g25 z ct_netref1 i/o schmitt, 12 ma (f) h.100/h.110 network reference 1. g26 z ct_netref2 i/o schmitt, 12 ma (f) h.100/h.110 network reference 2. c28 z ct_c8_a i/o schmitt, 12 ma (f) h.100/h.110 8 mhz clock a b28 z ct_c8_b i/o schmitt, 12 ma (f) h.100/h.110 8 mhz clock b c27 z ct_frame_a i/o schmitt, 12 ma (f) h.100/h.110 frame pulse a c26 z ct_frame_b i/o schmitt, 12 ma (f) h.100/h.110 frame pulse b e26 z ct_fr_comp o 12 ma (f) h.100/h.110 compatibility frame pulse d27 z ct_c2 o 12 ma (f) mvip 90-bit clock d28 z ct_c4 o 12 ma (f) mvip 90-bit clock times two e23 z ct_c16- o 12 ma (f) h-mvip 16 mhz clock d25 z ct_c16+ o 12 ma (f) h-mvip 16 mhz clock e27 z ct_sclk o 12 ma (f) scbus system clock e28 z ct_sclkx2 o 12 ma (f) scbus system clock times two f26 ct_mc i/o ttl, 12 ma (f) h.100/h.110 message channel. open collector output. e24 x mc_clock o 4 ma (f) h.100/h.110 message channel extracted clock. 2 mhz. nominal duty cycle: 62% high, 38% low. b27 mc_tx i ttl (f) h.100/h.110 message channel transmit data. when this signal is ?0?, the mt90503 will drive ct_mc low. when ?1?, the mt90503 will not drive ct_mc. c25 x mc_rx o 4 ma (f) h.100/h.110 message channel receive data. the level of this pin directly reflects the value of ct_mc. table 5 - h.100/h.110 bus interface pins
mt90503 data sheet 25 zarlink semiconductor inc. b25 ct_vdd5_0 i 5v power supply used in pci buffers of the ct_d[31:0] signals. can also be connected to 3v power supply. d20 ct_vdd5_1 i see ct_vdd5_0. d18 ct_vdd5_2 i see ct_vdd5_0. c17 ct_vdd5_3 i see ct_vdd5_0. pin rst name i/o type description e10 z recov_a i/o ttl, 4 ma (f) clock recovery general i/o a. this pin can be used as a gpio. d10 z recov_b i/o ttl, 4 ma (f) clock recovery general i/o b. this pin can be used as a gpio. c10 z recov_c i/o ttl, 4 ma (f) clock recovery general i/o c. this pin can be used as a gpio. b10 z recov_d i/o ttl, 4 ma (f) clock recovery general i/o d. this pin can be used as a gpio. e11 z recov_e i/o ttl, 4 ma (f) clock recovery general i/o e. this pin can be used as a gpio. d11 z recov_f i/o ttl, 4 ma (f) clock recovery general i/o f. this pin can be used as a gpio. c11 z recov_g i/o ttl, 4 ma (f) clock recovery general i/o g. this pin can be used as a gpio. b11 z recov_h i/o ttl, 4 ma (f) clock recovery general i/o h. this pin can be used as a gpio. table 6 - clock recovery pins pin nom switch (mhz) rst name i/o type description ae17 0 global_tri_state i ttl (f) (pu) should be 1 for functional mode, 0 for tristate. ah5 1 tck i ttl (f) jtag test clock. should be 1 when not in use ag5 1 tdi i ttl (f) jtag test data in. should be 1 when not in use ah4 1 x tdo o ttl, 4 ma (f) jtag test data out ag4 1 tms i ttl (f) jtag test mode select. should be 1 when not in use. ae7 1 trst i ttl (f) jtag test reset. should be 0 when not in use. table 7 - test pins pin rst name i/o type description table 5 - h.100/h.110 bus interface pins (continued)
mt90503 data sheet 26 zarlink semiconductor inc. pin rst name i/o type description h3 z txa_clk i/o ttl, 4 ma (f) utopia port a tx clock c6 z rxa_clk i/o ttl, 4 ma (f) utopia port a rx clock c2 phya_alm i ttl (f) phy alarm a this pin can also act as a gpi. d2 z phya_rx_led i/o ttl, 12 ma (f) led signal. when the led is on, this pin will be '0'. when the led is off, this pin will be tri-state. this pin can also act as a gpio. h5 z phya_tx_led i/o ttl, 12 ma (f) led signal. when led is on, this pin will be '0'. when the led is off, this pin will be tri-state. this pin can also act as a gipo. j5 1. txa_clav 2. txa_enb 1.i 2.i ttl (f) 1. utopia port a tx cell available (in atm) 2. utopia port a tx enable (in phy) h2 1.z 2.z 1. txa_enb 2. txa_clav 1.o 2.o 4 ma (f) 1. utopia port a tx enable (in atm). this pin must be pulled-up externally. 2. utopia port a tx cell available (in phy). this pin must be pulled-down externally. n2 z txa_soc o 4 ma (f) utopia port a tx start of cell l5, k2, k3, k4, k5, j2, j3, j4 z txa_data[7:0] o 4 ma (f) utopia port a tx data bus n4, n5, m2, m3, m4, l2, l3, l4 z txa_data[15:8] i/o ttl, 4 ma (f) utopia port a tx data bus each of these pins can be used as a gpio. n3 z txa_par o 4 ma (f) utopia port a tx parity a6 1. rxa_clav 2. rxa_enb 1.i 2.i ttl (f) 1. utopia port a rx cell available (in atm) 2. utopia port a rx enable (in phy) b6 1. z 2. z 1. rxa_enb 2. rxa_clav 1.o 2.o 4 ma (f) 1. utopia port a rx enable (in atm). this pin must be pulled-up externally. 2. utopia port a rx cell available (in phy). this pin must be pulled-down externally. h4 rxa_soc i ttl (f) utopia port a rx start of cell e2, e3, e4, d3, d4, d5, c5, b5 rxa_data[7:0] i ttl (f) utopia port a rx data bus g3, g4, g5, f1, f2, f3, f4, f5 rxa_data[15:8] i ttl (f) utopia port a rx data bus each of these pins can be used as a gpi. g2 rxa_par i ttl (f) utopia port a rx parity w4 z txb_clk i/o ttl, 4 ma utopia port b tx clock n1 z rxb_clk i/o ttl, 4 ma (f) utopia port b rx clock ab5 phyb_alm i ttl (f) phy alarm b this pin can also act as a gpi. w5 z phyb_rx_led i/o ttl, 12 ma (f) led signal. when led is on, this pin will be '0'. when the led is off, this pin will be tri-state. this pin can also act as a gpio. table 8 - utopia interface pins
mt90503 data sheet 27 zarlink semiconductor inc. t5 z phyb_tx_led i/o ttl, 12 ma (f) led signal. when led is on, this pin will be '0'. when the led is off, this pin will be tri-state. this pin can also act as a gpio. w2 1. txb_clav 2. txb_enb 1.i 2.i ttl (f) 1. utopia port b tx cell available (in atm) 2. utopia port b tx enable (in phy) w3 1z 2z 1. txb_enb 2. txb_clav 1.o 2.o 4 ma (f) 1. utopia port b tx enable (in atm) this pin must be pulled-up externally. 2. utopia port b tx cell available (in phy). this pin must be pulled-down externally. ad2 z txb_soc o 4 ma (f) utopia port b tx start of cell aa2, aa3, aa4, aa5, y2, y3, y4, y5 z txb_data[7:0] o 4 ma (f) utopia port b tx data bus ac3, ac4, ag2, ab2, ab3, ab4 z txb_data[13:8] i/o ttl, 4 ma (f) utopia port b tx data bus each of these pins can be used as a gpio. ac2 z 1. txb_data[14] 2. rxa_addr[4] 1.o 2.i ttl, 4 ma (f) 1. utopia port b tx data bus 2. utopia port a rx address 4 this pins can be used as a gpio. ad4 z 1. txb_data [15] 2. txa_addr[4] 1.o 2.i ttl, 4 ma (f) 1. utopia port b tx data bus 2. utopia port a tx address 4 this pin can be used as a gpio. ad3 z txb_par o 4 ma (f) utopia port b tx parity p4 1. rxb_clav 2. rxb_enb 1.i 2.i ttl (f) 1. utopia port b rx cell available (in atm) 2. utopia port b rx enable (in phy) p5 1.z 2.z 1. rxb_enb 2. rxb_clav 1.o 2.o 4 ma (f) 1. utopia port b rx enable (in atm). this pin must be pulled-up externally. 2. utopia port b rx cell available (in phy). this pin must be pulled-down externally. v2 rxb_soc i ttl (f) utopia port b rx start of cell t3, t4, r2, r3, r4, r5, p2, p3 rxb_data [7:0] i ttl (f) utopia port b rx data bus u3, u4, u5, t2 1. rxb_data [11:8] 2. rxa_addr [3:0] 1.i 2.i ttl (f) 1.utopia port b rx data bus 2. utopia port a rx address bus v4, v5, u1, u2 1. rxb_data [15:12] 2. txa_addr [3:0] 1.i 2.i ttl (f) 1. utopia port b rx data bus 2. utopia port a tx address bus v3 rxb_par i ttl (f) utopia port b rx parity ag10 z txc_clk i/o ttl, 4 ma (f) utopia port c tx clock af7 z rxc_clk i/o ttl, 4 ma (f) utopia port c rx clock ae10 1. txc_clav 2. txc_enb 1.i 2.i ttl (f) 1. utopia port c tx cell available (in atm). 2. utopia port c tx enable (in phy). pin rst name i/o type description table 8 - utopia interface pins (continued)
mt90503 data sheet 28 zarlink semiconductor inc. af10 1. z 2. z 1. txc_enb 2. txc_clav 1.o 2.o 4 ma (f) 1. utopia port c tx enable (in atm). this pin must be pulled-up externally. 2. utopia port c tx cell available (in phy). this pin must be pulled-down externally. ah9 z txc_soc o 4 ma (f) utopia port c tx start of cell ag9, af9, ae9, ah8, ag8, af8, ae8, ah7 z txc_data[7:0] o 4 ma (f) utopia port c tx data bus ag7 z txc_par o 4 ma (f) utopia port c tx parity ah6 1. rxc_clav 2. rxc_enb 1.i 2.i ttl (f) 1. utopia port c rx cell available (in atm) 2. utopia port c rx enable (in phy) aj6 1. z 2. z 1. rxc_enb 2. rxc_clav 1.o 2.o 4 ma (f) 1. utopia port c rx enable (in atm). this pin must be pulled-up externally. 2. utopia port c rx cell available (in phy). this pin must be pulled-down externally. ag6 1.z rxc_soc i ttl (f) utopia port c rx start of cell af6, ae6, af5, af4, ae2, ae3, af3, ad1 rxc_data[7:0] i ttl (f) utopia port c rx data bus ah10 rxc_par i ttl (f) utopia port c rx parity pin rst name i/o type description j25 pllvss_110 i vss pin for the ct pll. see figure 5, ?pll pin connections,? on page 34 for recommended connections. f28 pllvdd_110 i vdd pin for the ct pll. see figure 5, ?pll pin connections,? on page 34 for recommended connections. h26 plllp2_110 i loop-filter pin for the ct pll. see figure 5, ?pll pin connections,? on page 34 for recommended connections. g28 pllagn_110 o analog ground pin for the ct pll. see figure 5, ?pll pin connections,? on page 34 for recommended connections. ac5 pllvss_300 i vss pin for the fc pll. see figure 5, ?pll pin connections,? on page 34 for recommended connections. ag3 pllvdd_300 i vdd pin for the fc pll. see figure 5, ?pll pin connections,? on page 34 for recommended connections. table 9 - phase lock loop (pll) pins pin rst name i/o type description table 8 - utopia interface pins (continued)
mt90503 data sheet 29 zarlink semiconductor inc. pin rst name i/o type description e7 proc_out o process monitor pin output. must not be connected. table 10 - process monitor pins pin location pin location pin location pin location a2 gnd b9 n/c c16 ct_d[23] d23 ct_d[11] a3 vdd b10 recov_d c17 ct_vdd5_3 d24 n/c a4 gnd b11 recov_h c18 ct_d[24] d25 ct_c16+ a5 vdd b12 n/c c19 ct_d[12] d26 gnd a6 1. rxa_clav 2. rxa_enb b13 n/c c20 ct_d[22] d27 ct_c2 a7 gnd b14 n/c c21 ct_d[3] d28 ct_c4 a8 gnd b15 n/c c22 ct_d[9] d29 gnd a9 gnd b16 n/c c23 ct_d[1] e1 gnd a10 vdd b17 ct_d[31] c24 ct_d[7] e2 rxa_data[7] a11 vdd b18 ct_d[26] c25 mc_rx e3 rxa_data[6] a12 gnd b19 ct_d[27] c26 ct_frame_b e4 rxa_data[5] a13 n/c b20 ct_d[15] c27 ct_frame_a e5 n/c a14 vdd b21 ct_d[16] c28 ct_c8_a e6 gnd a15 gnd b22 ct_d[17] c29 vdd e7 proc_out a16 vdd b23 ct_d[14] d1 gnd e8 n/c a17 ct_d[30] b24 ct_d[6] d2 phya_rx_led e9 n/c a18 gnd b25 ct_vdd5_0 d3 rxa_data[4] e10 recov_a a19 vdd b26 ct_d[2] d4 rxa_data[3] e11 recov_e a20 vdd b27 mc_tx d5 rxa_data[2] e12 n/c a21 gnd b28 ct_c8_b d6 n/c e13 n/c a22 gnd b29 gnd d7 n/c e14 n/c a23 gnd c1 vdd d8 n/c e15 n/c a24 ct_d[5] c2 phya_alm d9 n/c e16 ct_d[25] a25 gnd c3 n/c d10 recov_b e17 ct_d[20] a26 gnd c4 n/c d11 recov_f e18 ct_d[21] a27 vdd c5 rxa_data[1] d12 n/c e19 ct_d[13] a28 gnd c6 rxa_clk d13 n/c e20 ct_d[4] a29 vdd c7 n/c d14 n/c e21 ct_d[18] table 11 - pin names listed by location
mt90503 data sheet 30 zarlink semiconductor inc. b1 gnd c8 n/c d15 n/c e22 ct_d[29] b2 vdd c9 n/c d16 ct_d[19] e23 ct_c16- b3 n/c c10 recov_c d17 ct_d[28] e24 mc_clock b4 n/c c11 recov_g d18 ct_vdd5_2 e25 n/c b5 rxa_data[0] c12 n/c d19 ct_d[8] e26 ct_fr_comp b6 1. rxa_enb 2. rxa_clav c13 n/c d20 ct_vdd5_1 e27 ct_sclk b7 n/c c14 n/c d21 ct_d[0] e28 ct_sclkx2 b8 n/c c15 n/c d22 ct_d[10] e29 gnd f1 rxa_data[12] j3 txa_data[1] l29 vdd p26 dmem_d[6] f2 rxa_data[11] j4 txa_data[0] m1 gnd p27 dmem_par[1] f3 rxa_data[10] j5 1. txa_clav 2. txa_enb m2 txa_data[13] p28 dmem_d[7] f4 rxa_data[9] j25 pllvss_110 m3 txa_data[12] p29 vdd f5 rxa_data[8] j26 dmem_a[9] m4 txa_data[11] r1 gnd f25 dmem_a[2] j27 dmem_a[10] m5 n/c r2 rxb_data[5] f26 ct_mc j28 dmem_a[4] m25 dmem_d[0] r3 rxb_data[4] f27 dmem_a[1] j29 gnd m26 dmem_d[2] r4 rxb_data[3] f28 pllvdd_110 k1 vdd m27 dmem_d[12] r5 rxb_data[2] f29 dmem_a[0] k2 txa_data[6] m28 n/c r11 gnd g1 gnd k3 txa_data[5] m29 gnd r13 gnd g2 rxa_par k4 txa_data[4] n1 rxb_clk r17 gnd g3 rxa_data[15] k5 txa_data[3] n2 txa_soc r19 gnd g4 rxa_data[14] k25 dmem_a[11] n3 txa_par r25 mem_clk_negative_i g5 rxa_data[13] k26 dmem_a[17] n4 txa_data[15] r26 mem_clk_positive_i g25 ct_netref1 k27 dmem_d[8] n5 txa_data[14] r27 dmem_par[0] g26 ct_netref2 k28 dmem_d[9] n11 gnd r28 dmem_a[12] g27 dmem_a[3] k29 vdd n13 gnd r29 gnd g28 pllagn_110 l1 vdd n15 gnd t1 vdd g29 gnd l2 txa_data[10] n17 gnd t2 1. rxb_data[8] 2. rxa_addr[0] h1 gnd l3 txa_data[9] n19 gnd t3 rxb_data[7] h2 1. txa_enb 2. txa_clav l4 txa_data[8] n25 dmem_d[3] t4 rxb_data[6] h3 txa_clk l5 txa_data[7] n26 dmem_d[13] t5 phyb_tx_led pin location pin location pin location pin location table 11 - pin names listed by location (continued)
mt90503 data sheet 31 zarlink semiconductor inc. h4 rxa_soc l11 gnd n27 dmem_d[4] t25 n/c h5 phya_tx_led l13 gnd n28 dmem_d[14] t26 dmem_a[13] h25 dmem_a[5] l15 gnd n29 dmem_d[5] t27 dmem_a[14] h26 plllp2_110 l17 gnd p 1 vdd t28 dmem_a[18] h27 dmem_a[7] l19 gnd p2 rxb_data[1] t29 gnd h28 dmem_a[8] l25 dmem_a[6] p3 rxb_data[0] u1 1. rxb_data[13] 2. txa_addr[1] h29 gnd l26 dmem_d[10] p4 1. rxb_clav 2. rxb_enb u2 1. rxb_data[12] 2. txa_addr[0] j1 gnd l27 dmem_d[1] p5 1. rxb_enb 2. rxb_clav u3 1. rxb_data[11] 2. rxa_addr[3] j2 txa_data[2] l28 dmem_d[11] p25 dmem_d[15] u4 1. rxb_data[10] 2. rxa_addr[2] u5 1. rxb_data[9] 2. rxa_addr[1] w26 1. cmem_a[18] 2. cmem_cs[1] ab28 cmem_d[1] ae11 reset u11 gnd w27 cmem_a[1] ab29 gnd ae12 inmo_d[15] u13 gnd w28 cmem_a[0] ac1 gnd ae13 gnd u15 gnd w29 vdd ac2 1. txb_data[14] 2. rxa_addr[4] ae14 inmo_d[7] u17 gnd y1 vdd ac3 txb_data[13] ae15 mem_clk_negative_o u19 gnd y2 txb_data[3] ac4 txb_data[12] ae16 inmo_d[1] u25 dmem_r/w y3 txb_data[2] ac5 pllvss_300 ae17 global_tri_state u26 dmem_bws [0] y4 txb_data[1] ac25 cmem_d[4] ae18 inmo_a[14] u27 dmem_bws [1] y5 txb_data[0] ac26 cmem_d[10] ae19 inmo_a[10] u28 dmem_cs[ 0] y25 cmem_cs [0] ac27 cmem_d[3] ae20 cpu_mode[0] u29 dmem_a[15] y26 cmem_bws [1] ac28 cmem_d[9] ae21 inmo_a[3] v1 gnd y27 cmem_bws [0] ac29 vdd ae22 n/c v2 rxb_soc y28 cmem_r/w ad1 rxc_data[0] ae23 n/c v3 rxb_par y29 vdd ad2 txb_soc ae24 cmem_a[15] v4 1. rxb_data[15] 2. txa_addr[3] aa1 gnd ad3 txb_par ae25 n/c v5 1. rxb_data[14] 2. txa_addr[2] aa2 txb_data[7] ad4 1. txb_data[15] 2. txa_addr[4] ae26 cmem_d[13] v25 dmem_cs [3] aa3 txb_data[6] ad5 gnd ae27 cmem_d[6] v26 dmem_cs [2] aa4 txb_data[5] ad25 gnd ae28 cmem_d[12] v27 dmem_cs [1] aa5 txb_data[4] a d26 cmem_d[5] ae29 gnd pin location pin location pin location pin location table 11 - pin names listed by location (continued)
mt90503 data sheet 32 zarlink semiconductor inc. v28 dmem_a[16] aa25 cmem_d[0] ad27 cmem_d[11] af1 gnd v29 vdd aa26 cmem_a[4] ad28 mem_clk_o af2 n/c w1 vdd aa27 cmem_a[3] ad29 mem_clk_i af3 rxc_data[1] w2 1. txb_clav 2. txb_enb aa28 cmem_a[2] ae1 gnd af4 rxc_data[4] w3 1. txb_enb 2. txb_clav aa29 gnd ae2 rxc_data[3] af5 rxc_data[5] w4 txb_clk ab1 gnd ae3 rxc_data[2] af6 rxc_data[7] w5 phyb_rx_led ab2 txb_data[10] ae4 n/c af7 rxc_clk w11 gnd ab3 txb_data[9] ae5 n/c af8 txc_data[2] w13 gnd ab4 txb_data[8] ae6 rxc_data[6] af9 txc_data[6] w15 gnd ab5 phyb_alm ae7 trst af10 1. txc_enb 2. txc_clav w17 gnd ab25 n/c ae8 txc_data[1] af11 mclk_src w19 gnd ab26 cmem_d[2] ae9 txc_data[5] af12 inmo_d[14] w25 n/c ab27 cmem_d[8] ae10 1. txc_clav 2. txc_enb af13 inmo_d[11] af14 inmo_d[6] ag11 interrupt2 ah8 txc_data[4] aj5 vdd af15 mem_clk_positive_o ag12 inmo_d[13] ah9 txc_soc aj6 1. rxc_enb 2. rxc_clav af16 inmo_d[0] ag13 inmo_d[10] ah10 rxc_par aj7 gnd af17 inmo_wr _r/w ag14 inmo_d[5] ah11 interrupt1 aj8 gnd af18 inmo_a[13] ag15 inmo_d[3] ah12 inmo_d[12] aj9 gnd af19 inmo_a[9] ag16 inmo_rdy_ndtack ah13 inmo_d[9] aj10 vdd af20 inmo_a[6] ag17 inmo_a le ah14 inmo_d[4] aj11 vdd af21 inmo_a[2] ag18 inmo_a[12] ah15 inmo_d[2] aj12 gnd af22 cpu_mode[3] ag19 inmo_a[8] ah16 inmo_rd_ds aj13 inmo_d[8] af23 n/c ag20 inmo_a[5] ah17 inmo_cs aj14 vdd af24 cmem_a[14] ag21 inmo_a[1] ah18 inmo_a[11] aj15 gnd af25 cmem_a[10] ag22 cpu_mode[1] ah19 inmo_a[7] aj16 vdd af26 cmem_par[0] ag23 cmem_a[17] ah20 inmo_a[4] aj17 inmo_a_das af27 cmem_d[14] ag24 cmem_a[13] ah21 inmo_a[0] aj18 gnd af28 cmem_d[7] ag25 cmem_a[9] ah22 cpu_mode[2] aj19 vdd af29 gnd ag26 cmem_a[7] ah23 cmem_a[16] aj20 vdd ag1 vdd ag27 cmem_par[1] ah24 cmem_a[12] aj21 gnd pin location pin location pin location pin location table 11 - pin names listed by location (continued)
mt90503 data sheet 33 zarlink semiconductor inc. ag2 txb_data[11] ag28 cmem_d[15] ah25 cmem_a[8] aj22 gnd ag3 pllvdd_300 ag29 gnd ah26 cmem_a[6] aj23 gnd ag4 tms ah1 gnd ah27 cmem_a[5] aj24 cmem_a[11] ag5 tdi ah2 gnd ah28 gnd aj25 gnd ag6 rxc_soc ah3 vdd ah29 vdd aj26 gnd ag7 txc_par ah4 tdo aj1 vdd aj27 vdd ag8 txc_data[3] ah5 tck aj2 gnd aj28 gnd ag9 txc_data[7] ah6 1. rxc_clav 2. rxc_enb aj3 vdd aj29 vdd ag10 txc_clk ah7 txc_data[0] aj4 gnd type input output i/o power ground n/c total utopia port a 21 12 12 45 utopia port b 21 14 10 45 utopia port c 12 12 2 26 clock recovery 0 0 8 8 cpu bus 26 3 16 45 tdm bus (h.100/h.110 bus) 1 9 39 4 53 control memory 0 23 18 41 data memory 0 26 18 44 data and control memory clocks 3 3 0 6 te s t 6 0 0 6 pll 1 1 0 2 2 6 power 40 40 ground 88 88 miscellaneous 1 1 no connects 49 49 total: 91 104 123 46 90 49 503 table 12 - pinout summary pin location pin location pin location pin location table 11 - pin names listed by location (continued)
mt90503 data sheet 34 zarlink semiconductor inc. figure 5 - pll pin connections 4.0 functional description 1 4.1 cpu interface the mt90503 cpu module provides an interface permitting programmability from an ex ternal microprocessor. the cpu module permits read/write access from mt90503: in ternal registers, internal and external memories. the cpu interface comprises of: ? direct access select (das) as the msb bit concatenated with a 15-bit address bus ? 16-bit data bus ? 2 interrupt signals ? associated control signals ? little endian format, unless otherwise specified the cpu interface can be configured to operate with either intel or motorola cpus. the mt90503 supports both 8-bit or 16-bit data bus and multiplex ed or non-multiplexed address/data pins. if the cpu is operating in 15-bit byte mode addressing with the lsb of its address bus as a byte field, then the inmo_a [14:0] pins of the mt90503 can be connected to the a[15:1] pins of the cpu. if both the mt90503 and the cpu are in 15-bit word mode addressing, then the inmo_a[14:0] pins should be conn ected to the a[14:0] pins of the cpu. a reduced set of registers ?cpu interface registers? ( 0000h to 000ah) are employed to optimize access time and to permit the cpu to execute indirect re ad/write accesses via these registers. the cpu also engages these registers to perform direct read/write accesses. the mt90503 and cp u timing relationship is described in section 9.1 on page 211. the cpu control register (0100h) provides a software rese t capability that allows the cpu to reset the mt90503 except for the cpu interface. the cpu inte rface can only be reset by a hardware reset. 1. this product incorporates technology licensed from melita international corporation. pllvdd_0 pllvss_0 pllvdd_1 pllvss_1 pllp2 pllagn 100pf 0.001uf 10uf vdd 100pf 0.001uf 10uf vdd 301 ohm (1%) 0.01uf (5%)
mt90503 data sheet 35 zarlink semiconductor inc. 4.1.1 cpu interrupts the cpu interface provides a programmable global interrupt capability. the interrupt signal names are ?interrupt1? and ?interrupt2?, pins ah11 and ag11 respectively. both interrupts have pr ogrammability to select their polarity (open collector drive) via registers ?interrupt1_conf? and ?interrupt 2_conf? addresses 0224h and 0226h respectively. interrupt1 accommodates a capability to program a mi nimum acceptable period between interrupts. the period is programmed in s units via ?interrupt1_conf? register. this provi des a ?frequency interrupt controller? facility and masks the assertion of further inte rrupts until the specified period has elapsed. the mask period will commence when the interrupt1_treated[15], register interrupt_flags address 0220h is set. when interrupt2 is enabled it is always activated when an interrupt condition occurs. interrupt pins are always tri-stated when inactive. the operation of the cpu interrupt network is common for all modules. when an interrupt is asserted an interrupt flag is set to identify the module where th e interrupt was generated. each module has one or more interrupt enable status registers where a set interrup t enable bit identifies the source of the interrupt. on completion of the isr the interrupt must be cleared as th e interrupt will remain asserted until it is de-asserted by the user. all interrupt enable status registers have a sym metrical status register. hence, the bit positioning of the interrupt enables and the associated status bits are identical. 4.1.1.1 example interrupt flow upon the initialization of the global in terrupt pins the following methodology is adopted to identify the source of the interrupt. for this example interrup t2 is employed and the cpu module w ill be the source of the interrupt. 4.1.1.2 interrupt initialization ? set interrupt polarity, register interrupt2_conf[15:14]. ? enable interrupt2 for the cpu module, register in terrupt2_enable[0] 022ch. the mt90503 will generate an interrupt on interrupt2 according to the modules enabled in interrupt2_enable. ? set the individual cpu interrupt sources by enabling the respective bits in the `status0_ie' 0104h register. within the `status0_ie' register there are two possi ble interrupt sources: internal_read_timeout_ie and inmo_read_done_ie. in the mt90503 register description the in terrupt bits are labelled ie (interrupt enable) in the ?type? column. this register offers the facility to mask/disable unwanted interrupts. 4.1.1.3 interrupt servicing when interrupt2 is asserted (?interrupt2? pin): ? read the interrupt flags to ascertain the module raising the interrupt. the cpu module interrupt flag is located in register interrupt_flags[0] 0220h, this bit is named cpureg_interrupt_active. ? if the cpureg_interrupt_active bit is set, locate the source of the cpu interrupt by reading the ?status0? register 0102h, either internal _read_timeout and/or inmo_read_done. ? the associated status register ?status0? 0102h contains internal_read_timeout and inmo_read_done bits. therefore, to de-assert the interrupt the user must write a 1 to register 0102h bits 3 or 4, internal_read_timeout and inmo_read_done respectively. only then will the interrupt be de-asserted.
mt90503 data sheet 36 zarlink semiconductor inc. 4.1.2 intel/motorola interface cpu_mode [3:0] interface type address pins data pins direct_access ale 0000 intel, 16 bit data bus, non-multiplexed inmo_a[14:0]** (word address) inmo_d[15:0] inmo_a_das inmo_ale* 0001 intel, 16 bit data bus, multiplexed inmo_d[15:1] (word address) inmo_d[15:0] inmo_a_das inmo_ale* 0010 intel, 8 bit data bus, non-multiplexed inmo_a[14:0] (byte address) inmo_d[7:0] inmo_a_das inmo_ale* 0011 intel, 8 bit data bus, multiplexed inmo_a[14:8]& inmo_d[7:0] (byte address) inmo_d[7:0] inmo_a_das inmo_ale* 0100 motorola, 16 bit data bus, non-multiplexed inmo_a[14:0] (word address) inmo_d[15:0] inmo_a_das inmo_ale* 0101 motorola, 16 bit data bus, multiplexed inmo_d[15:1] (word address) inmo_d[15:0] inmo_a_das inmo_ale* 0110 motorola, 8 bit data bus, non-multiplexed inmo_a[14:0] (byte address) inmo_d[7:0] inmo_a_das inmo_ale* 0111 motorola, 8 bit data bus, multiplexed inmo_a[14:8]& inmo_d[7:0] (byte address) inmo_d[7:0] inmo_a_das inmo_ale* 1xxx reserved * the inmo_ale pin is interpreted in all modes. however, it is not necessary in the non-multiplexed modes and can be tied to vc c. **the address placed on the inmo_a[14:0] pins is a word address in 16-bit mode and a byte address in 8-bit mode. the address, when placed on the inmo_d pins, is always a byte address. table 13 - cpu interface mode selection 0000h 0008h 000ah 0004h control register read/write da ta register address high register address low register the mt90503 cpu interface supports both intel and motorola microprocessors, in both 8-bit or 16-bit data bus and multiplexed or non-multiplexed address/data pins. the mt90503 supports 8 mb of addressable space, therefore indirection addressing is necessary. the microprocessor interface directly addresses five control words, used for indirection accessing. the indi rection register contents are shown in tables 13 to 17 incl usively. the timing relationship pertaining to the cpu interface registers and extended access is defined in section 9.1 on page 211.
mt90503 data sheet 37 zarlink semiconductor inc. field bit type reset description read_burst_length 6:0 rw 01h number of words to prefetch. setting words 00h 128 01h 1 02h 2 .. .. .. 7fh 127 this field is set to 01h for individual (non-sequential) reads. all burst reads greater than 256-bytes must be executed in two or more burst reads. reserved 7 ro 0h reset to 0. access_req 8 pc 0h set by software when an extended access is initialised. reset by hardware when the access is completed. used for extended indirect access only. extended_a[3:1] 11:9 rw 0h extended address bits 3:1. invalid for extended direct access. write_enable 13:12 rw 0h active high write enables. 00 = read access. 01 = write to lower byte. 10 = write to upper byte. 11 = write to entire word. this field is ignored for: extended direct reads and all byte wide extended direct accesses. extended_parity 15:14 rw 0h read/write parity bits. table 14 - control register (0000h) field bit type reset description extended_data[15:0] 15:0 rw 0000h the extended indirect read/write data word register. invalid for extended direct access. table 15 - read/write data register (0004h) field bit type reset description extended_a[32:20] 12:0 rw 000h upper extended address [32:20]. reserved 15:13 ro 0h reset to 000. table 16 - address high register (0008h) field bit type reset description extended_a[19:4] 15:0 rw 0000h lower extended address [19:4]. in extended direct addressing, bits 19:16 are employed for 16 bit data bus and bits 19:15 are employed for 8 bit data bus. table 17 - address low register (000ah)
mt90503 data sheet 38 zarlink semiconductor inc. 4.1.2.1 extended indirect accessing extended indirect accessing solely employs the register s 0000h to 000ah to access the 8 mb of addressable memory space. synopsis: the user writes the access address to registers 0000h, 0008h and 000a h. then the mt90503 will read/write to that address and fetch/place the data value from/to register 0004h. for all extended indirect accesses the inmo_a_das bit will be held low. 4.1.2.2 extended indirect writes the following steps must be executed to perform an extended indirect write: the software will set access_req [8] in register 0000h (step 4 above) and the hardware wi ll reset it when the data write has completed. therefor e, the user can poll this bit to dete rmine when the data write has completed. 4.1.2.3 extended indirect reads the software will set access_req[8] regi ster 0000h and the ha rdware will reset it when the data is ready to be read from register 0004h. 4.1.2.4 extended direct accessing extended direct accessing employs the high and low addre ss registers to perform page addressing. the address within the page is provided directly by the cpu address bus. similarly the data is fetched/placed directly on the cpu data bus. synopsis: the user writes the access address to re gisters 0008h and 000ah but this performs only the page addressing. upon assertion of the address within the page th e mt90503 will read/write the data with respect to that address. the inmo_a_das bit is set when the data read/write occurs. when operating the cpu interface in direct mode with a 16-bit data bus, extended_a[19:16], are employed for the lower address word register 000ah. 1 write the upper address, extended_a[32:20 ], to register 0008h. this write ma y be not be required if previous value holds true. 2 write the lower address, extended_a[19: 4], to register 000ah. this writ e may be not be required if previous value holds true. 3 write the write data, extended_data[15:0], to register 000 4h. this write may be not be required if previous value holds true. 4 write write_enable, extended_parity, access_req=?1? and extended_a [3:1] in a single access to register 0000h. 5 read the access_req bit located in the control regi ster[8] to determine when the write has completed. 1 write the upper address, extended_a[32:20 ], to register 0008h. this write ma y be not be required if previous value holds true. 2 write the lower address, extended_a[19: 4], to register 000ah. this writ e may be not be required if previous value holds true. 3 write write_enable = 00, access_req=?1? and extende d_a [3:1] in a single access to register 0000h. 4 wait until access_req is cleared, then read the data fr om the data field extende d_data[15:0], register 0004h. 5 optional parity check may be ascert ained by performing a read on t he extended_parity[15:14], register 0000h.
mt90503 data sheet 39 zarlink semiconductor inc. however, when operating the cpu interface in direct mode with an 8-bit data bus bits, [ 19:15] are used for the lower address word. 4.1.2.5 extended direct writes 4.1.2.6 extended direct reads 4.1.3 mt90503 reset procedure the following reset procedure is required to power- up the mt90503. the reset procedure must be adhered at power-up employing the reset pin. post power-up, the reset procedure can be performed from step 3. 1 write the upper address, extended_a[32:20 ], to register 0008h. this write ma y be not be required if previous value holds true. 2 write the lower address extended_a[19:16] or [19:15] to register 000ah. the remainin g bits [15:4] or [14:4] are ignored. this write may be not be re quired if previous value holds true. 3 write write_enable[13:12] (where a pplicable) and extended_parity[15:14]. the extended parity write is optional. 4 write the data value to the address within the corresponding memory page with the inmo_a_das bit set. 1 write the upper address, extended_a[32:20 ], to register 0008h. this write ma y be not be required if previous value holds true. 2 write the lower address, extended_a[19:1 6] or [19:15], to register 000ah. t he remaining bits [15:4] or [14:4] are ignored. this write may be not be re quired if previous value holds true. 3 assert the lower address within the memory page and fetch the read data with inmo_a_das set. 4 an optional read may be performed to obtain the parity values, extended_par ity[15:14] register 0000h. 1 assert the reset pin for at least 1000 mclk cycles. 2 de-assert the reset pin. all accesses in the remaining reset procedure wi ll employ indirection. 3 initialise the mem_clk_* bits and write_cache_e nable bit via the control register bits [13:10], address 0100h. 4 write the mclk_src frequency at register led1[6:0] and led flash frequency at registers led1[15:7], register address 0120h. write the le d flash frequency units (i.e. ms or s) at register led2[0], address 0122h. 5 initialise the pll via regi ster pll_conf, address 0128h. 6 set bits nreset_* in the contro l register bits [7:0], address 0100h. 7 initialize the data and control memory types via registers 0240h, 0242h, 0244h, 0248h, 024ah, and 024ch 8 select utopia clocking methodology at regi ster addresses 0230h, 0232h, 0234h and 0236h. 9 configure the interrupts? active_level for in terrupt1 and interrupt2 in register 0224h and 0226h.
mt90503 data sheet 40 zarlink semiconductor inc. 4.2 tdm module the general architecture of the tdm bus consists of three main elements. ? the tdm bus interface which is coupled directly to the bus pins and manages the timing requirements of the h.100/h.110 interface. ? the datapath management for transporting the bytes from the tdm bus to the circular buffers (located in the external data memory). ? the tdm clocking mechanism, this enables the mt90503 to be h.100/h.110 bus master capable and communicates with the clock recovery module. 4.2.1 tdm bus interface the mt90503 tdm module interfaces with all 32 data stream s of the h.100/h.110 bus. the maximum data rate of 8.192 mbps determines the total bus capacity of 4096 tdm tsst. the mt90503 can process up to: 2048 transmitting tdm tsst and 2048 receivi ng tdm tsst within one frame of 125 s. one less tdm channel is carried for each cas channel th at is desired. if all tdm channels have cas, then 1024 transmit and 1024 receive channels is the limit. the mt 90503 can drive out data on any particular tsst (time slot/stream), or read in dat a from any particular tsst. each individual time slot or ds 0 on the h.1x0 bus is assigned by a unique tsst number, based on the following equation: the timeslot ranges from 0 to 31 for 2mhz streams, fr om 0 to 63 for 4mhz streams, or from 0 to 127 for 8mhz streams. the 16 lowest data streams are cap able of running at a data rate lower than 8.192 mhz. the streams are grouped in fours and each quartet must run at the same data rate. streams [3:0], [7:4], [11:8] and [15:12] can each run at 2.048, 4.096 or 8.192 mhz as a group. this allows backward compatibility with older, slower tdm buses. in the reduced rate, the data is still latched using the ct_c8_a or _b clock-edge, but using ev ery second or every fourth clock-edge. the streams numbered [31: 16] must always run at 8.192 mhz. the tdm bus can also be configured to use only 4, 8, or 16 streams. this configuration requires less processing of tdm bytes and, also allows a reduced mclk speed. the 4-stream mode is useful for conducting tests, while the 16-stream mode allows mc lk speed to be cut in half wh ile still allowing half the bandw idth of a full h.100/h.110 bus. when the h.100/h.110 bus is carrying cas signalling bits , every even stream carries regular tdm data bytes, and is associated with an odd stream that carries cas bits and the indication of the begi nning of the multiframe. for tssts that are input to the mt90503, th e multiframing is provided by the fr amer. for tssts that are generated by the mt90503, the output multifra ming is provided by the mt90503; there is one multiframe which is common to all the t1 channel signals and one multiframe which is co mmon to all the e1 channel signals. on the input, the multiframing is independent for each tsst and the mt905 03 synchronises all of them to its multiframe. tsst = timeslot * 32 + stream (timeslot * 2+1) * 32 + stream (timeslot * 4+3) * 32 + stream for 8mhz streams for 4mhz streams for 2mhz streams
mt90503 data sheet 41 zarlink semiconductor inc. figure 6 - tdm serial to parallel/pa rallel to serial (spps) converter each tsst can be used independently for cas or regular td m bytes. for example, if time slot 0 on stream 0 requires signalling bits, then they will be carried on time slot 0, stream 1. ho wever, time slot 1 stream 1 can be used to carry normal tdm data, even if the time slot preceding it is used for signalling. t1 and e1 channel formats can be supported simultaneous ly. the multiframe bit?s po larity and position is programmable a nd global, and will be accepted at both the input and output. the cas bits occupy bits [7:4] or [3:0] of the cas byte, depending on the position within the byte of the multiframe indicator. the only difference between cas support in e1 or t1 mode is the number of frames in the multiframe. t1 contains 24 fr ames within its multiframes while e1 contains 16. the cas bits are latched at the input when the multiframe bit is active, and sent out on the output side during the entire multiframe. when the multiframe bit is at an active pola rity, the associated tdm byte is the first byte of the multiframe. figure 7 - cas and mfs transport on the tdm bus figure 7, cas and mfs transport on the tdm bus shows th e direct interface of the mt90503 with the tdm bus. tdm serial to parallel/parallel to serial module quad spps converter four ct_dx pins per spps, all running at the same frequency (2,4,8 mhz) spps0 tx tdm time- slot memory 32 x 32 bits rx tdm time- slot memory 32 x 36 bits quad spps converter four ct_dx pins per spps, all running at the same frequency (2,4,8 mhz) data transfer controler ct_c8_a ct_c8_b ct_frame_a ct_frame_b time-slot memory pointer synchronizer address control spps7 tdm data path controler tdm6.cdd fig tdm6 ct_c8 ct_d0 ct_d1 ct_frame a a bit 7 bit 6 a bit 5 a bit 4 a bit 3 a bit 2 a bit 1 a bit 0 a a sfs a?scas[3] ?scas[2]a?scas[1]a?scas[0] ct_c8 ct_d0 ct_d1 ct_frame a a bit 7 bit 6 a bit 5 a bit 4 a bit 3 a bit 2 a bit 1 a bit 0 a a bit 7 bit 6 a bit 5 a bit 4 a bit 3 a bit 2 a bit 1 a bit 0 a bit 7 bit 6 a bit 5 a bit 4 a bit 3 a bit 2 a bit 1 a bit 0 a a sfs a?scas[3] ?scas[2]a?scas[1]a?scas[0] a a sfs a?scas[3] ?scas[2]a?scas[1]a?scas[0] a sfs a?scas[3] ?scas[2]a?scas[1]a?scas[0]
mt90503 data sheet 42 zarlink semiconductor inc. the tdm interface is capable of looping back up to 2048 tssts with a latency of two tdm frames, or 250 s. this loopback is indicated by the control structures associated to each tsst. the loopback allows any two time-slots and streams to be connected together, and work i ndependently of the speed of each of the streams. the mt90503 can interface with 32 data streams as menti oned in previous paragraphs. since each tsst can be used to either send or receive data, the mt90503 must tri- state the ct_d pins that ar e receiving data. to avoid overlap between a sending and a receiving tsst, this must be done before the next one begins. 4.2.2 tdm bus clocking mechanism the mt90503 can operate as either a primary or secondar y h.100/h.110 master clock source. the h.100/h.110 clock (ct_c8) is driven by either ct_c8_a or ct_c8_ b. the mt90503 can generate the primary bus clock and all its associated bus clocks (ct_fr_comp, sclk, sclkx2, ct_c16-, ct_c16+, ct_c2 and ct_c4) by using the ct_netref signal. the ct_netref may be received from another h.100/h.110 bus compatible device or it can be determined by the clock recovery module. in master mode, the mt90503 will generate all the compatibility clocks that are necessary for co mmunicating with mvip and scsa tdm interfaces. these include the fr_comp, c2, c4 and c16 signals for communicating with mvip buses, and the sclk and sclkx2 signals for communicating with signal computing system architecture scsa buses. the tdm module monitors both ct_c8_a and ct_c8_b signals for clock properties and failure. in every operating mode, both the ct_c8_a and ct_c8_b signals are monitored for clock failure. there are two methods of detecting a clock failure on the bus. firstly, if the rising edge of the clock does not appear within 35 ns window of the expected period, the clock is flagged as being invalid . secondly, if a single frame does not contain exactly 1024 clock cycles, then the clock will fail. the mt90503 can be configured to switch to the backup master clock (ct_c8_a or ct_c8_b), upon the detection of a master clock failure. the mt90503 can be programme d as a secondary master and therefore switch to the backup master clock when the external primary master clock source has fail ed. if the mt90503 switches from a secondary master to master it will re-synchronise the tdm module with the backup clock and generate the compatibility clocks. the mt90503 continually monitors both ct_c8_a and ct_c8_b clocks for a failure condition. the mt90503 can be programmed to automatically swit ch to its backup clock in case of a failure. the mt90503 is an h.100/h.110 master-capable device and, therefore, is able to generate both ct_c8 clocks and ct_frame and compatibility signals. as long as the primary signals on the bus are valid, the mt90503 will synchronise its output to them using a pll. the mt90503 can also generate the ct_c8 and ct_frame signals independently of the pll, using the local 16 mhz clock. in this case, the output signals have no phase relation with those present on the bus. when the tdm bus interface module has written the receiv ed data to the circular buffers, it increments the time-slot memory pointer that is sent to the tx_sar. 4.2.3 tdm datapath when writing to the external data memory, no return val ue is expected. however, when reading data, a return value, upon storing the data into an rx tsst, is expected and is required to be written back to the structure memory. the underrun count, which may or may not have been updated, is always written back along with all the other bits of the second word. when the data is received at the time slot memory, it is sent via the tdm datapath to the external data memory. according to which time slot is currently bei ng used, the tdm contro l structures are read.
mt90503 data sheet 43 zarlink semiconductor inc. figure 8 - tdm data path controller when accesses are performed from the tdm channel asso ciation memory, the write back to the rx half of the circular buffer is also performed. when this write back is done, the underrun detection bit is written to ?0?, and a null-octet is inserted in place of the old data byte. the tdm datapath module can be configured to work wi th 32 h.100/h.110 streams, 16-streams, 8-streams, or 4-streams in order to allow lower clock speeds on the mt90503. the bandwidth requirements for supporting each of the above configurations are described in the bandwidth section. 4.2.4 tdm channel association structures tdm channel association structures are located at 0x8000 to 0xbffe in internal memory. each structure corresponds to a tdm channel by its tsst order. 4.2.4.1 non cas operation figure 9 - tdm channel association structures: tx channel non-cas mode tdm data path controler tdm channel a ssociation memory (2 x 2048 x 32 bits) data memory read access cache (64 x 48 bits) data memory write access cache (256 x 48 bits) tx tdm time-slot memories data memory dma controler rx tdm time-slot memories detect underruns (write back ur count field) w rite back address (for ur count) tx pointer rx pointer cpu address offset for mfs cpu write data write back data (for ur count) read data latch memory 64 x 48 bits data read process data write process ts0 ts7 ts5 b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 +2 1 tx/rx circular buffer address and size reserved mode tx/rx circular buffer address and size: address and size of the circular buffer in the data memory to which data bytes will be written. i : initialized bit. written by ?0? by software, set by hardware when the channel starts being treated. mode : channel mode of operation. ?0000?=normal pcm; others=reserved. rbw : rx byte write. selects byte that will be written in the low bytes of the data memory word where the tx tdm bytes are written. ?00?=do not write over the low byte; ?01?=write a null byte (usually ffh); ?10?=write silence pattern a; ?11?=write silence pattern b. rbw 0 i
mt90503 data sheet 44 zarlink semiconductor inc. the control structure in figure 10, tdm channel associ ation: rx channels (non cas mode) on page 44 indicates the mode and options selected for the tdm channel. in t he general tx structure, t he rbw (rx byte write) bits provide the format of the byte that is to be written over the rx byte in the circular buffer. while it is possible to write over the low-byte, there are three possibilities provided if writing over the byte is chosen: writing a null byte or generating one of two silence patterns. t he detailed description of the dual-dire ction buffer is provided in the tdm circular buffers section. figure 10 - tdm channel association: rx channels (non cas mode) in the receive direction, the control structure retains some of the recurrent features from the transmit structure. the tx circular buffer/size field is the sa me, which is normal given that the tx and rx circular buffers are common. the information on the address and size is encoded in the same way as in the tx structure. for the reception structure, the high mode bit codes wh ether the rx channel is transmitting a channel received from atm or if it is retransmitting information taken from the tdm bus and written into a circular buffer. if the high mode bit is ?0?, the channel is atm; if it is ?1?, the channel is tdm. by supporting a low latency tdm loopback, the mt90503 conforms to the h.100/h.110 specification. the c and u bits serve as status enable bits. these bits ar e r/w, and tell the register module whether the register counters and status bits should report errors on this vc. t he u bit is the underrun status enable: when this bit is set and an underrun is detected, the tdm register module w ill increment the global underrun counter and set the underrun detect status bit. the c bit serves at the cut vc detect status enable. when this bit is at ?0?, the ur count acts as a free running 256-underrun counter. in this case, it serves to compile the total number of underruns that have occurred. when the c bit is at ?1?, then the ur count serves as a detector for cut vcs. the counter resets to 0 each time a valid tdm byte is received. if an underrun is received, the counter is incremented by one. if the counter ever increments from 254 to 255, then 255 consecutive underruns have been received, indicating th ere is 32 ms of absent data. this is interpreted as a cut vc and will generate an interrupt. cell-loss integration periods of greater than 32 ms can be supported by software. upon ur count reaching 255, and subsequent interrupt to the cpu, the software can check that the count has not returned to zero (which happens if the cells start to arrive again) at some in terval equivalent to the ce ll-loss integration period. b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 +2 tx/rx circular buffer address and size reserved mode tx/rx circular buffer address and size : address and size of the circular buffer in the data memory f rom which data bytes will be read oe : voice stream output enable. this bit, when set, enables the driving of the voice data on the stream. mode : channel mode of operation. ?0000?=normal pcm; ?1000?=low latency loopback others=reserved. c : cut vc status enable. when ?0?, the ur count field is freerunning(256 consecutive underruns will not be considered as a cut vc). when ?1?, the ur count field is used as a consecutive underrun indicator that stops incrementing at 255. u : underrun status enable. when this bit is set and an underrun is detected, the status counters and bits w ill report this event. ur count : 8 bit underrun count. when the c bit is cleared, acts as a freerunning underrun error counter. w hen the c bit is set, it is used as a cut vc detector. in this mode, the counter is cleared each time a v alid byte is received. it increments (to a maximum of ffh) each time a byte underrun is detected. when a transition from feh to ffh occurs, the cut vc status register, counter and id fields are updated. must be initialized to ffh by software before enabling vc when c bit is set. must be initialized to 00h by software before enabling vc when c bit is cleared. 1 ur count u c oe
mt90503 data sheet 45 zarlink semiconductor inc. 4.2.4.2 cas operation figure 11 - tdm channel association: tx channels (cas mode) the rx byte write bits remain the same to allow the inse rtion of null patterns as for regular channels. the mode bits, indicate the possible configurati ons and combinations of multiframing and cas insertion: ?0100? is e1, ?0110? is t1, and toggling the lowest bit of either of the num bers indicates that the fastca s method of transmitting the data and cas bytes is being used. fastcas is used to lo wer the latency of circuit em ulation cells. when using the fastcas mode, the multiframe point er is not used and multiframe int egrity is therefore not maintained. in addition, special fields for cas are added in the two additional words of the struct ure. the cas we (cas write enable) bits are used to deter mine if the cas is written back. the tx_cas field is used so the cpu can insert values of cas, in place of values from the tdm bus; the rx cas value is used to compensate for underruns. the last tx cas field is used to detect when the ca s value received on the tdm bus has changed. when a cas value is received, it is written back to the last tx cas fi eld in the structure. whenever a new value arrives, it is compared to the last value. if there is a difference, a cas change signal is sent to the registers, and the new cas value is written to the cas change buffer in the external memory. the frame offset field is used to stor e the offset between the internal and exte rnal multiframes in the tx direction. when the tdm bus first obtains an external multiframe, it writes the offset field to the correct value between 0 and b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 +2 1 tx/rx circular buffer address and size reserved mode tx/rx circular buffer address and size : address and size of the circular buffer in the data memory to which data bytes will be written. i : initialized bit. written by ?0? by software, set by hardware when the channel starts being treated. mode : channel mode of operation. ?0100?=e1 strict multiframing; ?0101?=e1 fastcas; ?0110?=t1 strict multiframing; ?0111?=t1 fastcas; others=reserved. rbw : rx byte write. selects byte that will be written in the low bytes of the data memory word where the tx tdm bytes are written. ?00?=do not write over the low byte; ?01?=write a null byte (usually ffh); ?10?=write silence pattern a; ?11?=write silence pattern b. caswe : cas write enable. ?x0?=leave cas bits in rx circular buffer untouched; ?x1?=write rx cas ur in rx circular buffer in case of underrun; ?0x?=write cas bits present on the associated odd stream to the tx circular buffer; ?1x?=write tx cas force field in order to bypass the cas bits from the associated odd stream. tx cas force : tx cas value that must be written to bypass the cas bits from the associated odd stream. ei : cas enable ignore. if set, the cas enable bit (sfs bit) will be ignored. instead, the cas will be latched at one point for each 16/24 consecutive bytes (for e1 and t1 respectively). rx cas ur : rx cas value that will be sent in case of an underrun situation on the rx_sar side. cm : cas monitor. when ?1?, any change in the tx cas value will be reported to the cpu. last tx cas : last value of the tx cas received from the tdm bus. fs offset : frame offset that must be added in order for internal and external multiframes to coincide. initialize to ?00000? by software. rbw +4 +6 rx cas ur tx cas force caswe fs offset 0 last tx cas cm 00 ei i
mt90503 data sheet 46 zarlink semiconductor inc. 23. subsequently, each time that a byte is written to the circular buffer, the offset field is read, and an offset is established between the internal tdm pointer and the pointer that will be used. figure 12 - tdm channel association: rx channels (cas mode) the channel association structure for multiframe channels is slightly different, with only one bit being positioned differently in the structure. while the circular buffer addre ss and size field is still pres ent and functions in the same way, the mode bits are coded in the same way as they are in the transmit structure for multiframe channels. ?0100? is e1, ?0110? is t1, and toggling the lowest bit of ei ther of the numbers indicate s that the fastcas method of transmitting the data and cas bytes are employed. four new fields are added to allow for cas m anagement on the rx side with multiframing: ? last rx cas value that indicates the previous cas bits received on atm ? the cas monitor bit indicates if a change in th e value of cas is to be reported by the module ? man rx cas is the value of cas that can be inserted in the place of the one received. this value is only used if the me bit is set ? me bit manual cas insert b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 +2 tx/rx circular buffer address and size reserved mode tx/rx circular buffer address and size : address and size of the circular buffer in the data memory f rom which data bytes will be read oe : voice stream output enable. this bit, when set, enables the driving of the voice data on the even stream. mode : channel mode of operation. ?0100?=e1 strict multiframing; ?0101?=e1 fastcas; ?0110?=t1 strict multiframing; ?0111?=t1 fastcas; others=reserved. c : cut vc status enable. when ?0?, the ur count field is freerunning(256 consecutive underruns will be cosidered as a cut vc). when ?1?, the ur count field is used as a consecutive underrun indicator th t stops incrementing at 255. u : underrun status enable. when this bit is set and an underrun is detected, the status counters and bits will report this event cu : cas underrun enable. when this bit is set and an cas underrun is detected, the status counters and bits will report this ur count : 8 bit underrun count. when the c bit is cleared , acts as a freerunnin g underrun error counter. w hen the c bit is set, it is used as a cut vc detector. in this mode, the counter is cleared each time a v alid byte is received. it increments (to a maximum of ffh) each time a byte underrun is detected. when a transition from feh to ffh occurs, the cut vc status register, counter and id fields are updated. must be initialized to ffh by software before enabling vc when c bit is set. must be initialized to 00h by software before enabling vc when c bit is cleared. cm : cas monitor. when ?1?, any change in rx cas value will be reported to the cpu. when an underrun occurs, a cas change will never be reported. co : cas output enable. this bit, when set, enables the driving of the cas value out on the associated odd tdm steam. last rx cas : this is the value of the last rx cas sent on the tdm bus. this value is not written if an underrun has occured for this cas value, me : manual cas insert. when ?1?, the man rx cas is sent instead of the cas contained in the tl memory. man rx cas : cas value that is sent onto the tdm bus if me = ?1?. 1 ur count u c +4 +6 cu cm last rx cas man rx cas me 0 0 co oe
mt90503 data sheet 47 zarlink semiconductor inc. for both tx and rx channels, a change in the value of c as on a channel where the cas monitor bit is high will cause the new value to be written to the cas change buffer in the external memory. this buffer contains all the values that have been detected as diff erent from the previous value, along with the 12-bit ti me slot and stream value of the tdm channel to which they are associated. figure 13 - cas change structure in control memory the circular buffer address/size field is 15 bits and the addresses are 14 bits each, an indirect method of indicating the size is used. this is done by coding the size by the first ?1? that is encountered by reading the field starting from the left. for example, if the lowest bi t of the field is ?1?, the buffer is 128 bytes (mapped on a 256 byte boundary). if the lowest bit was ?0? but the second-lowest bit is ?1?, then the buffer is 256 bytes (mapped on a 512 byte boundary), etc. figure 14 - tx/rx circular buffer and size field b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 tsst number on which cas changed new cas fig tdm26 for 128 word buffers: b8 b9 b10 b11 b12 b13 b14 b0 b1 b2 b3 b4 b5 b6 b7 b16 b17 b18 b19 b20 b21 b8 b9 b10 b11 b12 b13 b14 b15 b0 b1 b2 b3 b4 b5 b6 b7 address of circular buffer in data memory for 256 word buffers: b8 b9 b10 b11 b12 b13 b14 b0 b1 b2 b3 b4 b5 b6 b7 b16 b17 b18 b19 b20 b21 b8 b9 b10 b11 b12 b13 b14 b15 b0 b1 b2 b3 b4 b5 b6 b7 address of circular buffer in data memory for 512 word buffers: b8 b9 b10 b11 b12 b13 b14 b0 b1 b2 b3 b4 b5 b6 b7 b16 b17 b18 b19 b20 b21 b8 b9 b10 b11 b12 b13 b14 b15 b0 b1 b2 b3 b4 b5 b6 b7 address of circular buffer in data memory for 1024 word buffers: b8 b9 b10 b11 b12 b13 b14 b0 b1 b2 b3 b4 b5 b6 b7 b16 b17 b18 b19 b20 b21 b8 b9 b10 b11 b12 b13 b14 b15 b0 b1 b2 b3 b4 b5 b6 b7 address of circular buffer in data memory 1 0 1 0 0 1 0 0 0 1 address[21:8] address[21:9] address[21:10] address[21:11] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fig tdm18
mt90503 data sheet 48 zarlink semiconductor inc. 4.2.5 tdm circular buffers the tdm module writes the data received from the bus to circular buffers that are as signed on a per-channel basis. the circular buffers? size is variable and is specifi ed in two places, i.e., once in the tdm channel association structure for which each channel has an entry, and once in the tx_sar or rx_sar structure which reads or writes to that channel. the tx part of the circular buffer (dat a read from the tdm bus and written to t he circular buffer) is contained in bits 15:8 of each circular buffer word. the rx part of the buf fer is contained in the remaining bits, 7:0. this alignment allows for underrun detection and null-pattern insertion in th e case of underruns. it also allows the detection of cut vcs. a cut vc is indicated when 256 consecutive underrun bytes are detected. in the non-multiframing mode, the circular buffers are used as a single block. this means that for each channel, up to 1024 bytes of data can be stored in the channel?s circul ar buffer. on the rx side, up to 128 ms of data can be stored for retrieval; therefore, at n = 1 with a packet size of 48 bytes, up to 61 ms of cdv can be compensated. in multiframing mode, each 32-byte divisi on of the circular buffer is used to store the information of one multiframe. in t1 operation, the first 24-bytes of the 32-byte division are used to reme mber the tdm data from the multiframe. in e1 operation, the first 16-bytes are us ed for the same purpose. in addition, in byte 31 of each division, the cas value of the multiframe is stored. in this way, the multif rame portion of the tdm pointer is valid for the tdm data and for the cas data; only the lowest bits need to be changed to ?11111? in order to point to cas. when write backs are performed, a null byte or one of tw o silent patterns (background noise) can be inserted in the rx byte. the silent patterns are read from buffers of up to 64 kb. these silent patterns can be used to generate noisy silences. figure 15 - silent pattern buffer a/b in control memory b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 pattern a byte 0 pattern b byte 0 +2 pattern a byte 1 pattern b byte 1 +4 pattern a byte 2 pattern b byte 2 +(n-2)*2 pattern a byte (n-2) pattern b byte (n-2) +(n-1)*2 pattern a byte (n-1) pattern b byte (n-1) the silent pattern buffer is n words long, n ranging from 0 to 65535.
mt90503 data sheet 49 zarlink semiconductor inc. figure 16 - tdm circular buffer (one multiframe in t1 mode) the cas bits are always kept in the highest four bits of the last byte. in addition to storing the data in the ci rcular buffers, the parity bits of th e data memory are used to detect underruns generated on the atm link. when the rx_sar writes data to the ci rcular buffers, it writes a ?1? in the parity bit of the memory?s low byte. when the tx_sar writes data bytes in the buffer, it writes a ?0? to the parity bit of the memory?s low byte. therefore, when the tdm reads the data from the circ ular buffer, it expects to read a ?1? from the parity bit. b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 op low byte ep high byte +2 +4 +6 +8 +10 +12 +14 +16 +18 +1a +1c +1e +20 +22 +24 +26 +28 +2a +2c +2e +30 +32 +34 +36 +38 +3a +3c +3e reserved tx byte 0 tx byte 1 tx byte 2 tx byte 3 tx byte 4 tx byte 5 tx byte 6 tx byte 7 tx byte 8 tx byte 9 tx byte 10 tx byte 11 tx byte 12 +a +c +e tx byte 13 tx byte 14 tx byte 15 rx byte 0 rx byte 1 rx byte 2 rx byte 3 rx byte 4 rx byte 5 rx byte 6 rx byte 7 rx byte 8 rx byte 9 rx byte 10 rx byte 11 rx byte 12 rx byte 13 rx byte 14 rx byte 15 underrun detection bits rx cas tx cas tx byte 16 tx byte 17 tx byte 18 tx byte 19 tx byte 20 tx byte 21 tx byte 22 tx byte 23 rx byte 16 rx byte 17 rx byte 18 rx byte 19 rx byte 20 rx byte 21 rx byte 22 rx byte 23
mt90503 data sheet 50 zarlink semiconductor inc. if it reads a ?0?, this means that an underrun has occu rred because not enough cells are being received, or there is too much cdv. figure 17 - tdm circular buffer (one super frame in e1 mode) b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 op low byte ep high byte +2 +4 +6 +8 +10 +12 +14 +16 +18 +1a +1c +1e +20 +22 +24 +26 +28 +2a +2c +2e +30 +32 +34 +36 +38 +3a +3c +3e reserved tx byte 0 tx byte 1 tx byte 2 tx byte 3 tx byte 4 tx byte 5 tx byte 6 tx byte 7 tx byte 8 tx byte 9 tx byte 10 tx byte 11 tx byte 12 +a +c +e tx byte 13 tx byte 14 tx byte 15 rx byte 0 rx byte 1 rx byte 2 rx byte 3 rx byte 4 rx byte 5 rx byte 6 rx byte 7 rx byte 8 rx byte 9 rx byte 10 rx byte 11 rx byte 12 rx byte 13 rx byte 14 rx byte 15 underrun detection bits rx cas tx cas
mt90503 data sheet 51 zarlink semiconductor inc. 4.2.6 tdm circular buffer pointers the convention that a write pointer points to a byte that is currently being written. in like manner, a read pointer points to a byte that is currently bei ng read. therefore, a read and write poi nter to the same buffer must never cross, or be equal to one another. 4.2.6.1 non-multiframing mode the global tdm_write_pointer points to the byte from t he tdm bus presently being writt en to the circular buffers. as in all modes, the tdm_read_pointer is increment ed before the tdm_write_pointer, because bytes that come from the tdm bus are written after the frame is complet ed. meanwhile, bytes read from the data memory and sent onto the bus are already transmitted by the time the frame is complete. the tdm_write_pnt sent to the tx_sar is the same as global tdm_write_pointer. the tdm_read_pnt sent to the rx_sar is one frame ahead of the global tdm_read_poi nter. since the tdm_read_pnt is one more than the global tdm_read_pointer, and the tdm_read_pointer is incremented before the tdm_write_pointer, the tdm_read_pnt will always have a lead of ei ther one or two over the tdm_write_pnt. figure 18 - tdm circular buffers (normal mode) b8 b9 b10 b11 b12 b13 b14 b15 +0 b0 b1 b2 b3 b4 b5 b6 b7 high byte low byte +2 +4 +6 +8 +a +c +e +10 +12 +14 +16 +18 +1a +1c +1e +20 +22 +24 +(n-3)*2 +(n-2)*2 +(n-1)*2 n=buffer word size {128,256,512,1024} tdm _ write_pnt tdm _ read_pnt rx byte (being read by tdm) rx byte (being written by tdm) ep op x 1 1 1 1 1 1 1 1 x 0 0 underrun detection bits rx_sar_write_pnt valid rx_sar_write_pnt positions valid tx_sar_read_pnt positions rx byte (being written by tdm) 0 0 0 0 0 valid tdm bytes waiting to be sent on the tdm bus 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tx byte (being written by tdm) tx_sar_ read_pnt valid tdm bytes wating to be sent in an a tm cell tdm _ lll_read_pnt
mt90503 data sheet 52 zarlink semiconductor inc. figure 18 tdm circular buffers (normal mode) shows that ve ry few of the positions with in the circular buffer are invalid for the sar pointers. 4.2.6.2 e1/t1 multiframing (standard) the tdm pointers change to respect the multiframing standar ds required by e1 and t1 operation. the pointer has two halves. one half indicates the number of the multiframe th at the tdm is writing or r eading; the other half is the number of the frame within the multifra me. in the t1 mode, this fraction goes from 0 to 23, while in the e1 mode it ranges from 0 to 15. the same global st andards of pointer definition still apply as the pointer still points to an invalid byte. the tdm_write_pnt has a global value, wh ich is the value of the internal mu ltiframe pointer. however, due to the multiframing offset, the tdm_write_pnt can vary by almost an entire frame. therefore, if the global tdm_write_pointer points to 0.0 (multi frame 0, frame 0) the individual tdm channels may be written anywhere from 0.0 to 0.23 in the t1 mode, and from 0.0 to 0.15 in the e1 mode. the tdm channels may be written almost an entire frame ahead of the global pointer. the poin ter sent to the tx_sar is the same as the global tdm_write_pointer. the tdm_read_pnt is two multiframes ahead of the tdm_writ e_pnt. the need for this lead arises from the write backs and from cas. since the tdm_write_pnt can be writ ing up to 15 frames ahead, a lead of at least one multiframe must be given. in addition to this, the cas mu st be considered. cas is written during the multiframe of the tx, which can be up to one multiframe ahead of the glo bal pointer. when cas is read from the rx side it is read at the beginning of the multiframe. theref ore, to ensure that there is always a difference of at least one in the cas pointers, the delta between the tdm pointers is established at two multiframes. furthermore, the read pointer that is sent to the rx_sar is almost one multiframe ahead. this is necessary because cas is sent at the end of the multiframe on the atm side, and is read at the b eginning of the multiframe on the tdm side. therefore, to ensure that the cas of the multiframe is writt en by the rx_sar before the tdm reads it, the pointer passed to the rx_sar is incremented by one multiframe minus one frame. therefore, if the tdm_read_pointer would have been 2.5 (two multiframes, five frames), the tdm_read_pnt passed to the rx_sar is 3.4 (three multifra mes, four frames).
mt90503 data sheet 53 zarlink semiconductor inc. ] figure 19 - tdm circular buffer (complete buffer in e1 mode, strict multiframing) figure 19 tdm circular buffer (complete buffer in e1 mode, strict multiframing) shows the tdm circular buffer in the e1 mode. the buffer is only half used for the tdm data. the cas is located at the end of the buffer, and the write and read pointers are offset by a full three multiframes. b8 b9 b10 b11 b12 b13 b14 b 15 +0 b0 b1 b2 b3 b4 b5 b6 b7 low byte high byte reserved rx multiframe 0 t x multiframe 0 +20 +40 rx multiframe 2 tx multiframe 2 +60 rx multiframe 3 tx multiframe 3 +80 rx multiframe 4 tx multiframe 4 rx multiframe (n/32)-2 tx multiframe (n/32)-2 +(n*2)-20 rx multiframe (n/32)-1 tx multiframe (n/32)-1 n=buffer word size {128,256,512,1024} +(n*2)-40 tdm_write_pn t (earliest) tdm_write_pn t (latest) tdm_cas_write_p nt (latest) tdm_cas_write_p nt (earliest) 15 byte offset tx_sar_read_pnt valid rx_sar_write_pnt positions valid tx_sar_read_pnt positions tx multiframe 1 tdm _ read_pnt tdm _ cas_read_pnt 2 mf offset rx multiframe 1 rx_sar_write_pnt 1 mf offset minimum
mt90503 data sheet 54 zarlink semiconductor inc. figure 20 - tdm circular buffer (complete buffer in e1 mode, fastcas) figure 20 tdm circular buffer (complete buffer in e1 mode, fastcas) is an e1 circular buffer in the fastcas mode. although the tdm read and write pointers are still significantly offset, t he delay has been reduced to nearly zero. this is because the rx_sar_write_pnt and the td m_read_pnt need only be offset by a single byte, as in non-multiframing mode. b8 b9 b10 b11 b12 b13 b14 b 15 +0 b0 b1 b2 b3 b4 b5 b6 b7 low byte high byte reserved rx multiframe 0 t x multiframe 0 +20 +40 rx multiframe 2 tx multiframe 2 +60 rx multiframe 3 tx multiframe 3 +80 rx multiframe 4 tx multiframe 4 rx multiframe (n/32)-2 tx multiframe (n/32)-2 +(n*2)-20 rx multiframe (n/32)-1 tx multiframe (n/32)-1 n=buffer word size {128,256,512,1024} +(n*2)-40 tdm_write_pn t (earliest) tdm_write_pn t (latest) tdm_cas_write_p nt (latest) tdm_cas_write_p nt (earliest) 15 byte offset tx_sar_read_pnt valid rx_sar_write_pnt positions valid tx_sar_read_pnt positions tx multiframe 1 tdm _ read_pnt tdm _ cas_read_pnt 2 mf offset rx multiframe 1 rx_sar_write_pnt 1 byte offset minimum
mt90503 data sheet 55 zarlink semiconductor inc. figure 21 - tdm circular buffer (complete buffer in t1 mode, strict multiframing) figure 21 tdm circular buffer (complete buffer in t1 mo de, strict multiframing) show s a t1 circular buffer in standard multiframing mode. the t1 circular buffer is identi cal to an e1 circular buffer except that the multiframes are 24 bytes instead of 16 bytes. b8 b9 b10 b11 b12 b13 b14 b 15 +0 b0 b1 b2 b3 b4 b5 b6 b7 low byte high byte reserved rx multiframe 0 tx multiframe 0 +20 +40 rx multiframe 2 tx multiframe 2 +60 tx multiframe 3 +80 tx multiframe 4 rx multiframe (n/32)-2 tx multiframe (n/32)-2 +(n*2)-20 rx multiframe (n/32)-1 tx multiframe (n/32)-1 n=buffer word size {128,256,512,1024} +(n*2)-40 tdm_write_pnt (earliest) tdm_write_pnt (latest) tdm_cas_write_pnt (latest) tdm_cas_write_p nt (earliest) 23 byte offset tx_sar_read_pnt valid rx_sar_write_pnt positions valid tx_sar_read_pnt positions tx multiframe 1 tdm _ read_pnt tdm _ cas_read_pnt 2 mf offset rx multiframe 1 rx_sar_write_pnt 1 mf offset minimum rx multiframe 3 rx multiframe 4
mt90503 data sheet 56 zarlink semiconductor inc. figure 22 - tdm circular buffer (complete buffer in t1 mode, fastcas) figure 22 tdm circular buffer (complete buffer in t1 mode, fastcas) shows a t1 circular buffer in fastcas mode. the t1 circular buffer is identical to an e1 circular buffer except for the fact that the multiframes are 24 bytes instead of 16 bytes. b8 b9 b10 b11 b12 b13 b14 b 15 +0 b0 b1 b2 b3 b4 b5 b6 b7 low byte high byte reserved rx multiframe 0 tx multiframe 0 +20 +40 rx multiframe 2 tx multiframe 2 +60 tx multiframe 3 +80 rx multiframe 4 tx multiframe 4 rx multiframe (n/32)-2 tx multiframe (n/32)-2 +(n*2)-20 rx multiframe (n/32)-1 tx multiframe (n/32)-1 n=buffer word size {128,256,512,1024} +(n*2)-40 tdm_write_pnt tdm_cas_write_pnt tx_sar_read_pnt valid rx_sar_write_pnt positions valid tx_sar_read_pnt positions tx multiframe 1 tdm _r ead_pnt tdm _ cas_read_pnt 2 mf offset rx multiframe 1 rx_sar_write_pnt 1 byte offset minimum rx multiframe 3
mt90503 data sheet 57 zarlink semiconductor inc. 4.3 tx_sar module 4.3.1 overview the purpose of the tx_sar module is to assemble tdm data bytes into atm cells to be transmitted to the utopia module. the tx_sar module has no external interfaces, and does not control any of the mt90503?s pins. however, it is the connecting block between the tdm mo dule and the utopia module in the data transmission direction. when the tx_sar assembles atm cells, it reads bytes from the circular buffers in data memory and uses these to assemble the atm cells. in order to transmit cbr atm cells correctly, a timing algo rithm is used to ensure that the atm cells are assembled and transmitted at the defined data rate . this timing algorithm is implemented using the transmit event scheduler. the transmit event scheduler is a construct in control memory that identifies the time atm cells need to be transmitted, and the circular buffer from which data for the atm cell is to be retrieved. atm cells are capable of carrying a variable number of virtual channels. t herefore, the rate at which ce lls are transmitted is variable. 4.3.1.1 support and trunking for different types of atm cells the type of atm cells the tx_sar supports includes aal1, cbr-aal0, and aal5-vtoa. the transmit event scheduler is capable of supporting the different data rates which are inherent to the different types of atm cells. figure 23 - atm cell formats shows the different form ats for the atm cells that the tx_sar module supports. the tx_sar is also capable of supporting hyperchannels (t runking) of up to 2048 channels per vc. in addition, it can also support aal0 and aal5 trunking, providing the number of channels is divi sible by the payload bytes. figure 23 - atm cell formats gfc vpi vpi vci vci vci pti cl hec csi seq crc p pp-byte payload byte #0 payload byte #1 payload byte #44 payload byte #45 gfc vpi vpi vci vci vci pti cl hec csi seq crc p payload byte #0 payload byte #1 payload byte #2 payload byte #45 payload byte #46 gfc vpi vpi vci vci vci pti cl hec payload byte #2 payload byte #3 payload byte #46 payload byte #47 payload byte #0 payload byte #1 gfc vpi vpi vci vci vci pti cl hec payload byte #2 payload byte #3 payload byte #0 payload byte #1 crc32 [31:24] length [15:8] length [7:0] "00000000" "00000000" payload byte #39 crc32 [23:16] crc32 [15:8] crc32 [7:0] aal1 with pointer cell 46 payload bytes aal5 cell 40 payload bytes aal0 cell 48 payload bytes aal1 without pointer cell 47 payload bytes
mt90503 data sheet 58 zarlink semiconductor inc. 4.3.2 tx_sar event schedulers 4.3.2.1 overview the purpose of the transmit event scheduler is to ensur e that the mt90503 assembles and transmits atm cells at the appropriate time. this timing function is implemented to reduce data overruns and underruns. before arriving at the tx_sar, tdm channel data is writt en into a variable-length (128 to 1024 bytes) transmit circular buffer, a construct in external data memory, by the tdm module. each tdm channel is assigned its own transmit circular buffer (see section 4.2.6 tdm circular buffer pointers). the transmit event schedulers determines when the information will be assembled into atm cells. the 15 transmit event schedulers are i dentical, and all have individual config uration registers. each transmit event scheduler is divided into a programma ble number of frames. when config ured correctly, each transmit event scheduler frame is constrained to an average of 125 s (i.e. the time required for one byte to be received/transmitted on each tdm channel). 4.3.2.2 the transmit event scheduler process please refer to figure 24 - transmit event schedule r process in conjunction with this subsection. the mt90503?s 15 transmit event schedulers are all mainta ined in a designated memory block in the external control memory. each transmit event scheduler can be progr ammed to support one of the four types of cells (aal1 with or without pointer, cbr-aal0, or aal5-vtoa). each of the trans mit event schedulers can be enabled or disabled via registers ( 0610h - 0616h) in order to use less bandwidth if a certain format of atm cell is not required. figure 24 - transmit event scheduler process provides an example of one of the 15 transmit event schedulers in the mt90503. all transmit event schedul ers have exactly the same properties, and all perform the same functions. they can be configured individually to handle different vc configurations. each of the 15 transmit event schedulers is made up of a number of ?frames?, with each frame containing a number of events. an event, if executed, consists of the assemb ling and placing in a utopia output fifo of one atm cell. the base address, length, and number of events can be programmed for each scheduler frame. each transmit event scheduler has its own scheduler base address which, in conjunction with an in ternal frame counter, will locate the events in a specific frame. in order for an atm cell to be assembled and transmitt ed at the appropriate time, the following transmit event scheduler process steps are required: an analogy can be made of the above process to a cont inuous ?spinning wheel?, where there is a continual selection and reading of events for each transmit even t scheduler frame. table 19 - scheduler event fields provides a description of the fields for one of the tr ansmit event schedulers. refe r to figure 24 - transmit event scheduler process to locate the fields. 1 on the reception of a frame puls e, the scheduler scans through t he events of the current frame. 2 for each valid event in the current frame, a cell is assembled and transmitted to the utopia module. 3 on the reception of the next frame pulse (125 s later) or upon the completion of the final valid event in the current frame, whichever is later, the scheduler in crements current frame, to point to the next frame in the scheduler. 4 the scheduler reads each frame sequ entially, returning to frame 0 upon completion of the final frame in the scheduler.
mt90503 data sheet 59 zarlink semiconductor inc. figure 24 - transmit event scheduler process scheduler 0?s info scheduler 1?s info scheduler 2?s info scheduler 14?s info 00000h 00008h 00010h 00070h i current frame num env read 2m events scheduler base address last frame (m) fields for the transmit transmit event frame 0 frame 1 frame 2 frame 3 frame m-2 frame m-1 frame m event 0 event 1 event m-1 event m b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tx structure address pointer sched num s event n-1 reserved b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 events never read fields for the scheduler event transmit event +2 +0 +6 notes : only 1 of 15 schedulers is shown m = 1 to 2048 frames per scheduler n = 0 to 45 events per frame frames within a scheduler are executed sequentially with a new frame beginning every 125 s (average). loops when last frame is read scheduler list scheduler format m = number of events in a frame that are read turn num +2 +0 event scheduler +0 +2n +4n +6n (m-2)*2n (m-1)*2n m*2n +4 transmit event scheduler list is located at the beginning of control memory
mt90503 data sheet 60 zarlink semiconductor inc. 4.3.2.3 transmit event scheduler fields description table 18 - field description fo r the transmit event scheduler provides a de scription of the fields for the transmit event scheduler. please refer to figure 24 - transmit event scheduler process to locate the fields. table 18 - field description for the transmit event scheduler field name of field bits used description of field i scheduler initialised bit +0/b15 this bit is reset by softwa re immediately before enabling the transmit event scheduler. hardware will set this bit the first time it reads the scheduler in formation structure. when the i bit is read at ?0? by hardware and the scheduler is used for t1/e1 support, the transmit event scheduler's current frame will be written between 0-23 for t1 and 0-15 for e1 in order for frame 0 to correspo nd to the first byte of a multiframe. turn num free run counter of scheduler wraps +0/b13:b11 turn num is a counter used for the implementation of multiframing. the scheduler re-s ynchronises itself with the multiframe count when turn num is 0. current frame current frame +0/b10:b 0 current frame is used to record the frame position of the transmit event scheduler. range 0 to (last frame) num env number of events per frame in the scheduler +2/b7:b5 the number of events per frame is 2 (num env)+1 . the same number applies to all frames in the scheduler. range:000 to 101 (2 to 63 events per frame). all others reserved. read 2m events read 2m first events +2/b4:b0 indicates to the scheduler how many events in each frame must be read. the same number applies to all frames in the scheduler. scheduler base address pointer to the beginning of the transmit event scheduler +4/b14:b0 this field is appended with "00000" as the lsbs, to form a 20-bit address. note : a frame must never cross a boundary of its own size in memory. therefore, if the transmit event scheduler has more than 8 events per fram e (32 bytes per frame), then some lsbs of this field must be 0. last frame (m) last frame (m) +6/b10:b0 last frame = (number of fram es in the scheduler) - 1. if last frame = 0, the scheduler is one frame long, if last frame = 1, the scheduler is two frames long, etc. m 0 1 2 . . 31 events read 64 2 4 . . 62
mt90503 data sheet 61 zarlink semiconductor inc. the number of events per frame in the scheduler, num en v, determines how much memory is allocated for each frame in the scheduler: 2 words per event. within this me mory, the scheduler will read only the first 2m events, as stored in the read 2m events field. of the events that are read, only those with t he scheduler num not equal to ?1111? (see table 19) are executed. no action is taken on events that are read wh ose scheduler num is ?1111?. 4.3.2.4 scheduler events fields description table 19 - scheduler event fields provi des a description of the fields for th e transmit event scheduler entries. figure 24 - transmit event scheduler process to locate the fields 4.3.2.5 bandwidth limitations for transmit scheduler events the maximum number of events per frame corresponds to t he maximum number of events that can occur in one frame of all the schedulers simultaneously. if the frames are not synchronised (as in figure 25 - unsyncrhonised sch edulers), the maximum number of events per frame is the sum of the maximum events in any frame of each scheduler (in this case, 32 events + 21 events = 53 events is the maximum number of events per frame). if the schedulers are synchronised (as in figure 26 - synchronised schedulers), the maximum num ber of events per frame is the worst in any particular frame (in this case, 23 + 17 = 40 events is greater than 6 + 24 = 30 events, so 40 events is the maximum number). if the schedulers are partially synchronised (as in figure 27 - partially synchronised sc hedulers), the maximum number of events per frame is the worst in any frame that can po ssibly align (in this case, 20 + 5 = 25 events is less than 27 + 12 = 39 events which is greater than 20 + 16 = 36 event s and 27 + 7 = 34 events so 39 events is the maximum number). field name of field bits used description of field scheduler num transmit event scheduler number +0/b5:b2 this field contai ns the scheduler number. 0000 to 1110 = valid scheduler numbers 1111 = invalid event. no action will be taken on this event the transmit event schedulers are read sequentially. s start bit +0/b0 this field indicates the first event that will be carried out when the vc is initialised. software must set the s bit of only one event once programming of the scheduler is complete. this bit is only relevant until th e i bit is set in the tx control structure. after the i bit is set, all events with valid scheduler numbers will be executed as they are encountered. tx structure address pointer tx structure address pointer +2/b14:b0 this field is the pointer to the tx_sar structure used to assemble an atm cell each time this event is read. this field is appended with "00000" as the lsbs to form a 20-bit address. table 19 - scheduler event fields transmission speed maximum number of events per frame 25 mbps 7 155 mbps 45 622 mbps 183 table 20 - maximum number of events per frame for common transmission speeds
mt90503 data sheet 62 zarlink semiconductor inc. figure 25 - unsyncrhonised schedulers figure 26 - synchronised schedulers figure 27 - partially synchronised schedulers 4.3.3 out of bandwidth error the tx_sar out-of-bandwidth error indica tes that a particular region of t he scheduler, or the scheduler as a whole, is overloaded. this error occurs when the tx_sar lagging by f frames or more, where f is an integer written to register 0608h. the tx_sar has 125 s to execute all the events in the frame it is servicing at the current time. if all the events in the frame are not executed within 125 s, the tx_sar continues until the end of the current frame before moving on to events in the next frame. this method reduces the amount of time it has to service the following frame. if the first frame took 150 s to service, then there would only be 100 s left to service the following frame. therefore, if the second frame is also very full, the tx_sar would not have the time to finish servicing it and will be late again for the following frame. if frames take an excessively long time to service, the mt90503 may become several frames late. if the mt90503 detects that it is f or more frames late, an out-of-ba ndwidth error will be declared and the mt90503 will skip the next f frames of events. this action will cause latency in the transmission delay and corrupt data on the vcs until the channel reconverges. the channel reconverges once every 375 frames (47 ms) in ?aal1 with pointer? schedulers, and less often if multiframing is used. the ce lls that were supposed to be assembled in the f missing frames are skipped, and new cells are assembled with the ol d data. the out-of-bandwidth error arises from an error 21 events 9 events scheduler 1 frame 1 frame 0 26 events 15 events 32 events scheduler 0 frame 0 frame 2 frame 1 23 events 6 events scheduler 0 frame 1 frame 0 17 events 24 events scheduler 1 frame 1 frame 0 frame 1 frame 0 20 events 27 events scheduler 0 frame 1 frame 0 5 events 12 events frame 3 frame 2 16 events 7 events scheduler 1
mt90503 data sheet 63 zarlink semiconductor inc. with the mapping of the transmit event scheduler. despite this error, the mt 90503 will continue with its operations, however, some cells may be lost. 4.3.3.1 percent of bandwidth register the tx_sar incorporates a percent of bandwidth register (0510h), which indica tes the maximum number of mclk cycles utilised by the tx_sar process per frame. the pe rcent of bandwidth register counts the number of mclk cycles from the time that a frame is received, to the time that all the entr ies for that frame in the schedulers have been completely handled. this value will be compared to the current maximum value obtained by the tx_sar process. if the most current value is higher, it is reta ined and written into the percen t of bandwidth register. the value in the percent of bandwidth register can be clear ed by the software. if the tx_sar takes more than 125 s to assemble the cells of a particular frame, the percent of bandwidth register?s value will be greater than the number of mclk cycles in the 125 s time frame. 4.3.3.2 distribution of events by software the events in the transmit event scheduler need to be dist ributed as evenly as possible. for example, an ?aal1 with pointer? 3-channel vc has three ev ents per 46.875 frames. these events must be spaced out with a distance of 15 or 16 frames between events to prevent irregular data dist ribution resulting in transmission latency and/or data integrity problems. consequently, a scheduler 8 * 46.875 = 375 frames in length containing 24 events is required to map the three events per 46 .875 frames evenly. the mapping of this information is accomplished by external software. one of the key features of the transm it event schedulers is their programmabl e length. since different cells require different sizes of schedulers, the sch edulers are capable of handling any sc heduler length from 1 to 2048 frames. refer to table 21 for examples of transmit event scheduler sizes. 4.3.4 mapping of the transmit event scheduler with the ?aal1 with pointer?, the format for the mapping of the transmi t event scheduler is asymmetric. the ?aal1 with pointer? format expects a cell ev ery 46.875 frames per channel, a transmit event scheduler with 47 frames that skips the last frame one turn out of eight is required. the mt90503 overcomes this difficulty by creating an extended transmit event scheduler of 375 frames, which is 8 * 46.875. therefor e, the irregularity of the transmit event scheduler is corrected and events can be mapped appropriately. due to this multiplication, the number of events mapped in the transmit event scheduler for any vc is always a multiple of eight. this means the firs t event in the transmit event scheduler is always a p-byte event and contains a zero value pointer indicating the start of a structure. atm cell type number of frames transmit event scheduler size in kb (e.g. 32 events per frame) cbr-aal0 48 6* aal1 with pointer 375 47 aal1 without pointer 47 5.875 aal5-vtoa/cbr-aal0 240 30 e1 with cas 750 94 t1 with cas 1125 141 *note: 6 kb = 32 events per frame * 48 frames per scheduler * 4 bytes per event table 21 - examples of typical transmit event scheduler sizes
mt90503 data sheet 64 zarlink semiconductor inc. 4.3.5 tx_sar control structures tx_sar control structures are constructs in control me mory which contain atm cell information. when a frame event is read from one of the 15 transmit event schedulers, an atm cell is assembled. the scheduler event contains the base address that points to the control structure that is used for assembling the atm cell. the control structure contains all of the fields t hat are required for assembling the atm ce ll. the destination field in the control structure is responsible for telling the utopia module t he destination vc of the assembled atm cell. for detailed information regarding the desti nation field, refer to table 22, 'descripti on of the fields for the tx_sar control structure"? on page 65. figure 28 - tx_sar event scheduler pointer flow and c ontrol structure shows a func tional block diagram of an example of transmit event scheduler interconnections and pointer flow to the tx_sar control structure. figure 28 - tx_sar event scheduler pointer flow and control structure scheduler 0?s info 00000h 00008h 00070h scheduler list scheduler 0 event 0 scheduler 0, frame 1 scheduler 0, frame 0 scheduler 0, frame 1 scheduler 0, frame 374 pointer to current frame in scheduler header of the tx_sar control structure structure tdm channel 2 pnt tdm channel 1 pnt tdm channel 0 pnt tsst 0 tsst 1 tsst 2 tsst 4093 tsst 4094 tsst 4095 event 1 event 63 tx_sar_read_pnt tdm channel association memory (internal) tdm_write_pnt tx side rx side tdm channel 1?s circular buffer (in the data memory) byte written by tdm transmit byte read by tx_sar note: all structures are in the cont rol memory unless otherwise specified tx/rx circular buffer pointer (same pointer in channel association memory and in tx_sar control structure) base address of control structure from event 1
mt90503 data sheet 65 zarlink semiconductor inc. 4.3.5.1 tx_sar control structure fields figure 29 - tx_sar control structure shows the tx_sar co ntrol structure format and data fields held in control memory. table 22, description of the fields for the tx_sar control structure de scribes the data fields. the header for the atm cell to be constructed is derived fr om words +8 and +a in the tx_sar control structure. the final 8 bits of the cell header, the header error c heck (hec), are calculated and inserted by the utopia module. the channel entries, be ginning at +16h, are 14-bit poi nters to the circular buffers in external data memory, one for each channel in the vc. figure 29 - tx_sar control structure field name of field byte address offset /bits used description of field first entry first entry +0/b15:b12 fi rst entry gives the position within the structure of the pointer to the first channel. the field is a word pointer and is constant with a value of 0xb. to allow for future structure updates, its value is programmable. channel 0?s address is located at base_add + (2 * first entry). a structure active +0/b11 this bit indicates whether or not the vc is active. the control structure becomes active when a is set. the a bit is set by software. if the a bit is reset, th e control structure will always be ignored. if the a bit is set, ha rdware may ignore it for other reasons, such as the control structure not being initialised. table 22 - description of the fields for the tx_sar control structure first entry a srts aal ce bs last entry txd payload size offset gfc vpi vci [15:12] vci [11:0] oam clp p-byte counter current entry i seq tx_sar_read_pnt transmitted cell counter [31:16] transmitted cell counter [15:0] channel 0?s tx/rx circular buffer pointer channel 1?s tx/rx circular buffer pointer channel (n-2)?s tx/rx circular buffer pointer channel (n-1)?s tx/rx circular buffer pointer reserved n=number of tdm channels in the vc hardware write back fields b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 + 0h + 2h + 4h + 6h + 8h + ah + ch + eh + 10h + 12h + 14h + 16h + 18h +(n*2) + 14h + (n*2) + 16h header fields pti v v v v
mt90503 data sheet 66 zarlink semiconductor inc. srts synchronous residual time stamp +0/b8:b7 the srts bits indicate the generation of srts within the vc. srts is either absent, enabled, or enabled and master. many vcs can be programmed to transmit srts, but only one can request a new srts value. if many vcs transport srts, they must all be of the same size , i.e., the same number of channels, to ensure the validity of the values. if srts is generated on the vc, it is packaged within the aal1 byte of cells 1, 3, 5 and 7 of an 8-cell cycle. the srts field should never be enabled on cbr-aal0 or aal5-vtoa vcs. if srts is enabled on multiple vcs, the events must be mapped in such a way that an event that generated cell # 0 for the master vc occurs before the event that generates cell # 0 for all the other vcs. the srts field bits are encoded as follows: 00 = no srts 01 = reserved 10 = send srts 11 = send srts, and request a new srts value on seq = 7 aal adaptation layer +0/b6:b5 the aal bits indicate the atm format to be used to assemble the cells in this structure. the aal field bits are decoded as follows: 00 = cbr aal0. consists of cbr data 01 = aal5-vtoa. includes a crc and a payload size indicator at the end of the cell 10 = aal1 without pointer. includes a sequence number packaged with the cell, as well as the possibility of transmitting srts on the vc 11 = aal1 with pointer. includes a sequence number packaged with the cell, and the pos sibility of transmitting srts on the vc field name of field byte address offset /bits used description of field table 22 - description of the fields for the tx_sar control structure (continued)
mt90503 data sheet 67 zarlink semiconductor inc. ce circuit emulation +0/b4:b2 the ce field bits indicate the presence of a multiframing standard used within the vc. the multiframing standard changes the way the information is read from the tdm circular buff ers, as well as the standard that is used to generate the p-by te. in addition, setting the ce bits to a cas setting will indicate to the tx_sar that cas signaling bits must be inserted at the end of the aal1 control structure. the field bits are decoded as follows: 000 = no cas, no multiframe 001 = reserved 01x = reserved 100 = t1 without cas (t1 type circular buffer, but no cas will be sent in the atm cells) 101 = t1 with cas (t1 type circular buffer, with cas sent in the atm cells 110 = e1 without cas (e1 type ci rcular buffer, but no cas will be sent in atm cells) 111 = e1 with cas (e1 type circular buffer, with cas sent in the atm cells bs tx/rx circular buffer size +0/b1:b0 these bits encode the size of the tdm circular buffer that is to be read from. in t1 and e1 modes, a portion of space in the circular buffer is required to store the cas values; in the t1 mode 25% is required, and in the e1 mode 50% is required. half of the tdm circular buffer is used for tx data and half for rx data. the field bits are decoded as follows: 00 = 128 words 01 = 256 words 10 = 512 words 11 = 1024 words last entry last entry +2/b15:b4 last entry is the word offset from the 8 kb boundary containing the structure to the last circular buffer pointer in the structure. txd tx_sar destination field +2/b3:b0 the txd field is used to tell the utopia module the destination of the assembled atm cell. the tx_sar destination field is decoded as follows: 0000 = discard atm cell 0xx1 = send to txa port 0x1x = send to txb port 01xx = send to txc port others = reserved broadcasting to multiple ports is allowed. field name of field byte address offset /bits used description of field table 22 - description of the fields for the tx_sar control structure (continued)
mt90503 data sheet 68 zarlink semiconductor inc. payload size payload size +4 /b15:b10 for fully-filled cells, regardless of type, the payl oad size field is 30h. for partially-filled cells, th e payload size indicates the number of tdm bytes to be placed in each atm cell. the field range is from 4h to 2fh. note : 2fh is an illegal value for partially-filled aal1cells for partially-filled aal5 vtoa, this field must be set to 8h, 10h, 18h, 20h, or 28h. offset offset +4/b9:b3 offset is used when the vc first starts up, and whenever an event with the s bit is set in the transmit event scheduler entry. this shows the delta that must exist between the tx_sar read pointer and the tdm write pointer within the circular buffer. the value for this offs et will change de pending on the number of channels in the vc, and on the multiframing standard used. offset?s value is programmed with the maximum number of bytes of a given channel in an atm cell, plus three. if an error is produced when programming offs et, a global tx _slip will be flagged in the register 0 502h, indicating an erroneous configuration and the possibi lity of corrupted data. the offset between the tx_wrt_pnt (tdm) and the tx_sar_read_pnt that must be present prior to assembling any atm cell whose event in the transmit event scheduler has the s bit set. this offset is coded as an integer from normal vcs. it is coded as an multi-frame [1:0] and frame [4:0] number for e1 and t1 vcs. gfc, vpi, vci, oam, pti, clp header information +8, +a/b15:b0 header information for the cells to be assembled using this tx_sar control structure. p-byte counter p-byte counter +c/b14:b0 the p-byte counter field is us ed for the generation of the p-byte within the cell, or within the multiframe structure. the p-byte counter is decremented each time a byte of data is sent, including a cas byte, but not including an information byte such as the aal1 byte or the pointer-byte. whenever the counter reaches 0 and must decrement, its value is reset to p-byte max field which must be set to 0 by the software. whenever a p-byte needs to be generated, the seven lsbs of the p-byte counter are the value of the p-byte, with parity added as the msb. the decrementing continues until the value of the p-byte counter reaches 0 and wraps around again, ending the multiframe and beginning a new one. field name of field byte address offset /bits used description of field table 22 - description of the fields for the tx_sar control structure (continued)
mt90503 data sheet 69 zarlink semiconductor inc. 4.3.6 miscellaneous tx_sar features 4.3.6.1 t1 with cas and e1 with cas cell format mapping for the transmission of t1 with cas and e1 with cas, the number of frames required is 9000 and 6000 respectively. but, because the number of frames mapped in a full size transmit event scheduler is always a multiple of eight, the mt90503 handles large size sched ulers by dividing the size by eight, and mapping eight times less events (1125 for t1 with cas and 750 for e1 with cas). this results in a latency of one frame. current entry current entry +e/b15: b4 the current entry field tells the sar what the first channel is to be assembled in this cell. the valid values for this field are contained between the first entry and the last entry fields inclusively. the current entry field also points to words, and is initialised by software to the word pointed to by the first entry field. the the current entry field is similar the last entry field, such that it is defined as the offset between the current entry field and the 8 kb boundary in which the structure is contained. i structure initialised bit +e/b3 the i bit is set by the hardw are when a scheduler entry flagged with the start bit asserted high is encountered, i.e., as soon as the first cell is sent on this vc. this bit is cleared by the software upon initialisation. seq aal1 sequence number +e/b3:b0 these bits are reset by software. tx_sar_read_ pnt tx_sar_read _pnt +10/b15:b6 this value is a pointer to t he next byte to be read in the tx/rx circular buffers. transmitted cell counter free running transmitted cell counter +12, +14/b15:b0 the transmitted cell counter increments each time a cell is transmitted on the vc. the time needed for the counter to wrap-around decreases proportionately with the numbe r of channels in the vc. this field should be reset by software and is used for monitoring. vtdm channel valid +16 to end/b15 when this bit is high the channel is active. when this bit is ?0?, the programmable null byte, found in register 0420h, will be transmitted. channel n's tx/rx circular buffer pointer channel n's tx/rx circular buffer pointer +16 to end/b13:b0 this field is a pointer to the tx/rx circular buffer associated with this channel. "0000 0000" will be appended to this field as the lsbs to form a 22-bit address in data memory. field name of field byte address offset /bits used description of field table 22 - description of the fields for the tx_sar control structure (continued)
mt90503 data sheet 70 zarlink semiconductor inc. 4.3.6.2 support of partially-filled cells the mt90503 is capable of supporting partially-fill ed cells, as long as the number of channels in the vc is smaller or equal to the cell fill. a single transmit event schedul er can be created to accomm odate several sizes of aal1, cbr-aal0 or aal5-vtoa atm cells. aal1 with pointer atm cells can be used by this format, since the number of data bytes per atm cell is always constant. for exampl e, the 240-entry transmit event scheduler is capable of accommodating partially-filled cells of 4-, 5-, 6-, 8-, 10-, 12-, 15-, 16-, 20-, 24-, 30-, or 40-bytes per cell. 4.3.6.3 tx_sar fifo the tx_sar transmits cells contained in its data cell fi fo when there are no events to be processed. the tx sar?s data fifo can be used to store aal0 cells as well as oam cells, therefore, cpu-based oam cell generation is supported. 4.4 rx_sar module the rx_sar module performs processing on atm cells received from the utopia module. cells placed in the rx_sar input fifo by the utopia module are read, proc essed, and then written into the appropriate multi-cell circular buffer in external control memory. the processi ng involves identifying the vc corresponding to the cell, examining the cell for errors, determining where to place the data, and monitoring the status of circular buffers. the rx_sar module also directs data cells to the data cell fifo from which the cpu can read them. the rx_sar module does not connect to any external pi ns, interfacing instead with the utopia module, cpu interface, and external memory controller . global pointers are shared between the rx_sar and tdm modules. atm cells that are received by the mt90503 are processed by the utopia module and can be directed to any of three tx output fifos or to the 32-ce ll rx_sar input fifo. those cells that are forwarded to the rx_sar are directed to the sar portion (cells to be formatted into tdm streams), to the da ta cell portion (to be examined by the cpu), or to both. for cells directed to the sar portion, the rx_sar uses control information in the rx_sar control structures (section 4.4.2) to extract the payload data from the received cell and store it into tdm channel rx circular buffers located in external data memory. 4.4.1 treatment of data cells data cells, such as those containing oam information, are placed in a programmable length fifo in external control memory. the length of the fifo is stored in regi ster 070eh. the cpu can read a data cell at any time, after obtaining the address of the fifo (registe r 070ch) and the read pointer (register 0708h). the cpu can be alerted to the presence of data cells via an in terrupt that triggers if either of two events occur: the interrupt can be generated when the fifo becomes more than half full or the interrupt can be generated if a data cell has been present in the fifo for longer than a programmable period of time (registers 0720h, 0722h). this interrupt can be enabled through register 0220h. when ready to process the information, the cpu obtains a read pointer to the informat ion from register 0708h and reads the information through 26 word accesses. cells with the oam bit set in the pti portion of the header can be directed to the data cell fifo on a per vc basis. the same is true for non-oam cells. in addition, unknown non-oam cells, and/or unknown oam cells can also be sent to the data cell fifo (all unknown non-oa m cells are directed to the same location(s)). 4.4.2 control structure for each vc directed to the sar portion of the rx_sar, an rx_sar control structure exists in external control memory. the structure, similar to that of the tx_sar, contains information on how to process a cell including: ? what type of traffic is being carried (aal1, cbr-aal0, aal5-vtoa)
mt90503 data sheet 71 zarlink semiconductor inc. ? the size of the circular buffers for the data ? how to act in the case of an overrun or underrun ? the multiframing standard in place ? expected presence of cas ? enabled errors, the size of the payloads ? information necessary to detect and correct for errors ? a pointer to each circular buffer, one for each channel in the vc figure 30 - rx_sar control structure field name of field byte address offset/bits used description of field first entry first entry +0/b15:b12 f irst entry field give s the position within the structure of the pointer to the first channel. the field is a word pointer and is constant with a value of 0xb. to allow for future structure updates, its value is programmable. channel 0?s address is located at base_add + (2 * first entry). table 23 - description of the fields for the rx_sar structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b1 b0 last entry se le ae pe fc ce im bs aal first entry max used bytes in rx circular buffer payload size p -byte counter pbi current entry rx_sar_write_pnt ilast seq 2nd last seq monitored min lead monitored max lead slip free rx_sar_write_pnt received cell co unter [31:16] reserved n = number of tdm channels in the vc v v v v received cell counter [15:0] channel 0?s tx/rx circular buffer pointer channel 1?s tx/rx circular buffer pointer channel (n-2)?s tx/rx circular buffer pointer channel (n-1)?s tx/rx circular buffer pointer b2 +0 +2 +4 +6 +8 +a +c +e +10 +12 +14 +16 +18 +(n*2)+14 +(n*2)+16
mt90503 data sheet 72 zarlink semiconductor inc. aal adaptation layer +0/b8:b7 the aal bits indicates the atm format used to assemble the cells in this structure. the aal bits are decoded as follows: 00 = cbr aal0 01 = aal5-vtoa 10 = aal1 without pointer 11 = aal1 with pointer bs tx/rx circular buffer size +0/b6:b5 these bits encode the size of the entire tx/rx circular buffer that is to be written into. in t1 and e1 modes, a certain portion of the space in the buffer is required to store the cas values; in the t1 mode 25% is required and in the e1 mode 50% is required. the eight msbs of each word in the tx/rx circular buffer are used for tx data and the remaining 8 bits for rx data. these bits are decoded as follows: 00 = 128 words 01 = 256 words 10 = 512 words 11 = 1024 words im initialisation method +0/b4 initialisation method for rx_sar_write_pnt '0' = initialise rx_sar_write_ pnt to nearest boundary: either tdm_read_pnt + (max used bytes in tx/rx circular buffer) - 1 or tdm_read_pnt + 1 '1' = initialise rx_sar_write_pnt to (max used bytes in tx/rx circular buffer)/2 this initialisation method will be used when the first cell is received and each time a slip (an overrun or underrun) occurs. ce circuit emulation +0/b3:b1 the circuit emulation bits indicate the multiframing standard used within the vc. these bits are decoded as follows: 000 = no cas, no multiframe 001 = reserved 01x = reserved 100 = t1 without cas 101 = t1 with cas 110 = e1 without cas 111 = e1 with cas fc fastcas enable +0/b0 fastcas is enabled when fc is asserted high. if fastcas is used, then the receive pointer used for regular tdm bytes and for cas bytes is not the same. cas is written one multiframe before tdm bytes in fastcas. when fc is deasserted, regular multiframing is employed: cas is written in the same multiframe as tdm bytes. last entry last entry +2/b15:b4 last entry is the word offset from the 8 kb boundary containing the structure to the last circular buffer pointer in the structure. se slip error report enable +2/b3 when set, overrun and underrun slips will generate an rx_sar error report structure (figure 32) in the error fifo in control memory. field name of field byte address offset/bits used description of field table 23 - description of the fields for the rx_sar structure (continued)
mt90503 data sheet 73 zarlink semiconductor inc. le cell loss and insertion error report enable +2/b2 when set, single cell loss es, multiple cell losses and cell misinsertions will generate an rx_sar error report structure (figure 32) in the error fifo in control memory. ae aal1 byte report enable +2/b1 when set, aal1 crc-3 and crc-3/seq num parity errors will generate an rx_sar error report structure (figure 32) in the error fifo in control memory. pe p-byte error report enable +2/b0 when set, p-byte parity errors, p-byte absent and p-byte framing errors will generate an rx_sar error report structure (figure 32) in the e rror fifo in external control memory. max used bytes in rx circular buffer max used bytes in rx circular buffer +4/b15:b6 this field indicates the range of valid positions in bytes of the rx_sar_write_pnt relative to the tdm_rx_read_pnt before a cell is received. in no case can this value be 0. payload size payload size +4/b5:b0 for fully-filled cells, regardless of type, the payload size field is 30h. for partially-filled cells, the payload size indicates the number of tdm bytes in each atm cell. the field range is from 4h to 2fh. note : 2fh is an illegal value fo r partially-filled aal1cells for partially-filled aal5 vtoa, this field must be set to 8h, 10h, 18h, 20h, or 28h. pbi p-byte initialization +6/b15 initialized to ?0? by software. p-byte counter p-byte counter +6/b14:b0 this field is a counter used to detect p-byte framing errors. when a p-byte is detected, this counter is loaded with the p-byte?s value. each time a tdm byte is received, the counter is decremented. w hen the counter reaches the current entry it should be reset to the first entry and the rx_sar_write_pnt should point to the beginning of the multiframe if applicable. when it decrements below 0, the counter resets to its maximum. any time a p-byte is received, its value should match the value in this field, or a p-byte framing error will be detected. current entry current entry +8/b11:b0 current entry indicates which tdm channel the rx_sar is currently writing to the circular buffers. the current entry is defined as being the offset from the 8 kb boundary containing the structure and the ?tx/rx circular buffer pointer? being read from the structure. current entry is initialised to the value of first entry, increments up to last entry, and then wraps around to first entry. this field should be initialised by software to 0bh. note : this field should not be written to while the vc is active. field name of field byte address offset/bits used description of field table 23 - description of the fields for the rx_sar structure (continued)
mt90503 data sheet 74 zarlink semiconductor inc. memory containing the control structures is divided into 8 kb blocks. zero or more control structures can exist in a block. control structures must be fu lly contained in a single block. the po inters current entry and last entry are relative to the 8 kb block boundary in which their structure resides. the buffer size (bs) field indicates t he size of the receive circular buffers. though the buffer size is indicated in words, the received data occupies only the lower byte of each word; the data to be transmitted occupies the upper bytes. selection of size: 128, 256, 512, or 1024 words, depends on the amount of available memory and on the cdv for the vc. the receive half of the buffer must be ca pable of holding twice the maximum cdv (peak cdv) plus the packetisation size of the cells in the vc plus two additional bytes. additional sp ace must be added if e1 or t1 formats are employed (the buffer must be twice as big for e1 and a 4/3 of the size for t1). to convert the maximum cdv from ms into bytes, a data rate of 8000 bytes/s mu st be applied. the packetisatio n size is defined as the maximum number of bytes a channel can contain in a single cell of the vc. to find the maximum cdv supported by the buffer, the valu e of the "max used bytes in circular buffer" field must be divided by two and multiplied by 125 s/byte. because a larger buffer will cause more delay through the rx_sar, the choice of the value of "max used bytes in ci rcular buffer" must be made as a compromise between the cdv supported and the delay inserted by the rx_sar. in the t1/e1 multiframe mode, the value of "max used bytes in circular buffer" must be an integer number of frames and is counted in a multiframe/frame fashion. the rx_sar_wr ite_pnt rx_sar write pointer +a/b15:b4 this is a pointer to the location where the next byte will be written in each tx/rx circular buffer. it is common to all tx/rx circular buffers controlled by the rx_sar control structure. in the e1/t1 mode, this field is divided in multiframe [6:0] and frame[4:0]. only the lower pa rt of the field is used to point to the tx/rx circular buffer. i structure initialised bit +a/b3 this bit must be reset by software before enabling the vc in the lut. the bit is set by hardware after receiving the first cell. last seq last seq +a/b2:b0 last received aal1 sequence number. 2 nd last seq 2 nd last seq +c/b2:b0 second-last received aal1 sequence number. slip free rx_sar_wr ite_pnt slip-free rx_sar write pointer +10/b15:b4 the slip-free rx_sar_w rite_pnt is the same as the rx_sar_write_pnt except that slips (overruns and underruns) do not affect its value. received cell counter received cell counter +12/b15:b0 +14/b15:b0 a 32-bit free running cell counter us ed for monitoring activity on a vc and for statistical purposes. this field can be initialis ed to '0' by software. v tdm channel valid +16 to end/b15 when this bit is high the channel is active. when this bit is reset, all received bytes on the channel are discarded. channel n's tx/rx circular buffer pointer channel n's tx/rx circular buffer pointer +16 to end/b13:b0 this field is a pointer to the tx/rx circular buffer associated with this channel. "0000 0000" will be appended to this field as the lsbs to form a 22-bit address in external data memory. field name of field byte address offset/bits used description of field table 23 - description of the fields for the rx_sar structure (continued)
mt90503 data sheet 75 zarlink semiconductor inc. five msbs select a number of multiframes and the five lsbs a number of frames. in stri ct muliframing, the five lsbs are always set to '00000'; they can be any value in fastcas. setting the multiframing standard in the circuit emulation (ce) field will change the way the information is read from the tdm circular buffers, as well as t he standard that is used to interpret the p-byte. in addition, setting the ce bits to a cas setting will indicate to the rx_ sar that c as signalling bits should be expected at the end of the aal1 structure. the payload size represents the number of tdm bytes in the cell and does not include pointer or aal1-bytes. 4.4.3 errors within the four categories of errors, there are eleven possible errors. al l but slip errors (overruns and underruns) pertain only to aal1 cells. for the following errors, the only action taken is the gen eration of an error report st ructure (section 4.4.4): ? crc errors ? crc/sequence number parity errors ? multiple cell loss ? p-byte parity format tdm bytes bytes transmitted payload size aal1 with pointer, non-p-type cell 16 17 16 aal1 with pointer, p-type cell 16 18 16 cbr-aal0 16 16 16 table 24 - payload sizes for various cell formats category error coverage example aal1 byte crc error aal1 cells crc/sequence number parity error aal1 cells csi = 1, crc = 010, seq. num = 110, parity bit = 1. even parity not observed: a parity error has occurred. cell loss/misinsertion single cell loss aal1 cells sequence numbers 1, 2, 4 received. cell 3 has been lost cell misinsertion aal1 cells sequence number s 1, 2, 4, 3 received. a cell misinsertion has occurred multiple cell loss aal1 cells sequence numbers 1, 2, 5 received. cells 3, 4 have been lost. p-byte errors p-byte parity error aal1 cells p-byt e = 0100110, parity bit = 0. even parity not observed: a p-byte parity error has occurred p-byte out-of-range aal1 cells p -byte received = 0x52, structure length for that vc = 0x18. p-byte is too large p-byte framing error aal1 cells p-byt e is 0x15 when 0x17 was expected. p-byte absent aal1 cells slip errors overrun all cells see figure 31. underrun all cells see figure 31. table 25 - rx_sar errors
mt90503 data sheet 76 zarlink semiconductor inc. ? out-of-range ?framing ? absent errors it is the responsibility of the cpu and associated softwa re to act upon notification that an error has occurred. the exceptions to this policy are ? single cell loss (a dummy cell is inserted and treated before accepting the received cell; the received cell counter is incremented by only one) ? cell misinsertion (the misinserted cell is discarded and the received cell counter is not incremented) ? overruns (data is lost and read/write pointers are adjusted) ? underruns (bytes are inserted according to informat ion set in registers 0420h and read/write pointers are adjusted). . figure 31 - overrun and underrun examples 4.4.4 error report structure four categories of errors can be enabled in the rx_sar structure: ? slip errors ? cell loss & misinsertion errors ? aal1 byte errors ? p-byte errors for each cell containing an error for which the error catego ry is enabled, an 8-byte error report structure is generated and stored in a fifo in external control memo ry. from here, the cpu can read the fifo and treat the errors. invalid byte overrun max used bytes in rx circ. buff. invalid byte valid byte valid byte valid byte valid byte invalid byte tdm read pointer rx_sar write pointer valid byte valid byte valid byte valid byte underrun max used bytes in rx circ. buff. invalid byte tdm read pointer rx_sar invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte invalid byte valid byte valid byte valid byte invalid byte invalid byte invalid byte invalid byte invalid byte tdm read pointer rx_sar write pointer normal max used bytes in rx circ. buff. invalid byte write pointer note: for a description of max used bytes in circular buffer see table 23 (+4/b15:b6).
mt90503 data sheet 77 zarlink semiconductor inc. as per the data cell fifo, the cpu can read the error fi fo at any time after obtaining the address to the fifo (registers 0714h, 0716h) and the read pointer to the rx _sar error report structure (register 0710h). again, an interrupt can be generated that will tr igger if either of two events occurs: wh en the fifo becomes more than half full or if an error report structure has be en present in the fifo for longer than a programmable period of time (register 0724h, 0726h). this interrupt c an be enabled in register 0220h. errors of more than one type on the same cell will re sult in one error r eport structure being created indicating all types of errors on that cell. the exception to this is cell misinsertion. since the cell is discarded once the misinsertion has been detected, no further errors can be found on the misinserted cell. figure 32 - rx_sar error report structure field name of field byte address offset/bits used description of field rx_sar structure base address [19:5] rx_sar structure base address [19:5] +0/b14:b0 base address of the rx _sar control structure that caused the error report structure to be generated. appended with "00000" as the lsbs to form a 20-bit address. seq sequence number +2/b2:b0 sequence number of the cell that caused the error report structure to be generated. last seq last sequence number +2/b5:b3 sequence number of the cell which preceded the one that caused the error report structure to be generated. received cell counter received cell counter +4/b15:b0 +6/b15:b0 cell number of the cell that caused the error report structure to be generated. pa p-byte absent error +0/b15 a p-byte was expected but was not detected in the cell that caused the error. pf p-byte framing error +2/b15 the p-byte that was detected did not match the p-byte that was expected. pr p-byte range error +2/b14 the p-byte that was detected was out-of-range; the 7-bit p-byte must not be 94-126 and must be less than the sequence length of the corresponding vc. 127 signifies a dummy offset value. pp p-byte parity error +2/b13 the p-byte detected did not match its parity bit. ac aal1 byte crc-3 error +2/b12 there was an error detected in the crc-3. ap aal1 byte parity error +2/b11 the aal1 byte detected did not match its parity bit. table 26 - description of the fields for the rx_sar error report structure received cell counter [15:0] received cell counter [31:16] last seq seq rx_sar structure base address[19:5] pf pr pp ac ap or ur m ml sl pa b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b1 b0 b2 +0 +2 +4 +6
mt90503 data sheet 78 zarlink semiconductor inc. or overrun slip +2/b10 the circular buffer associated with a channel receiving data from the cell was overrun. ur underrun slip +2/b9 the circular buffer associated with a channel receiving data from the cell was underrun. m cell misinsertion +2/b8 the sequence num ber of the cell indicated that a cell was misinserted. this error is always preceded by a single cell loss. ml multiple cell loss +2/b7 the sequence number of the cell indicated that multiple cells were lost. sl single cell loss +2/b6 the sequence numbe r of the cell i ndicated that a single cell was lost. table 26 - description of the fields for the rx_sar error report structure (continued)
mt90503 data sheet 79 zarlink semiconductor inc. 4.5 utopia module 4.5.1 overview the purpose of the utopia module is to provide an external interface with the atm domain. the mt90503 complies with the atm forum?s specifications: af-p hy-0017.000 and af-phy-0039.000. the mt90503 uses octet-level handshaking on its utopia interface. the utopia module is responsible for accepting cells fr om four input interfaces, examining the cells and, based on the source and information in the header, sending the cell to one or more of the four output interfaces. the utopia module also calculates and appends the hec to outgoing atm cells. figure 33 - utopia module the utopia interface consists of three ports, labelled a, b, and c. port a is a level-2 atm (single phy), single phy or multi-phy port and can operate at 50 mhz. port b is a level-2 atm (single ph y) or single phy port and can operate at 50 mhz. it is restricted to an 8-bit data bus when port a is in multi-phy mode. port c is a level-1 atm or phy port. in addition to ports a, b, and c, the utopia accepts ce lls from the tx_sar and routes cells to the rx_sar and to the data cell fifo in external control memory. 4.5.2 utopia interfaces each of the three ports is divided into two portions: a receive portion and a transmit portion. the tx_sar and the receive portions are each connected to a 4-cell fifo. these fifos are read on a round-robin basis by the cell router (see ?cell router? on page 82.). the rx_sar and the transmit portions are each connected to a 32-cell fifo. the ports are configurable with the following options: ? port a?s transmit portion can be atm, phy, with a 16-bit or 8-bit data bus. append rx structure pointer aal1 byte a b control memory interface cell fifo (32 cells) cell fifo (32 cells) cell fifo (32 cells) cell fifo (32 cells) cell fifo (4 cells) cell fifo (4 cells) cell fifo (4 cells) cell fifo (4 cells) txa utopia interface (external) txb utopia interface (external) txc utopia interface (external) rx_sar interface (internal) rxa utopia interface (external) rxb utopia interface (external) rxc utopia interface (external) tx_sar interface (internal) srts and adaptive clock recovery interface rxa_clk domain rxb_clk domain rxc_clk domain txa_clk domain txb_clk domain txc_clk domain mclk domain unknown cells match & mask lut discard known cells cell router
mt90503 data sheet 80 zarlink semiconductor inc. ? port a?s receive portion can be atm or phy, with a 16-bit or 8-bit data bus. ? port a can be level-2 multi-phy. ? port b?s transmit portion can be atm or phy, with a 16-bit or 8-bit data bus.* ? port b?s receive portion can be atm or phy, with a 16-bit or 8-bit data bus.* ? port c?s transmit portion can be atm or phy, with an 8-bit data bus. ? port c?s receive portion can be atm or phy, with an 8-bit data bus. * when port a is in level-2 multi-phy m ode, port b must have an 8-bit data bus. each receive interface ca n be independently enabled or disabled. if disabled, the receive interface will stop accepting cells after the current cell has been received. when the transmit portions of a port are in phy mode, t he soc, data bus, and parity output pins can be tristated when the port is not selected. this allows the mt90503 to share a data bus, soc, and parity lines with other devices (i.e. independent enb signals and clav signals fo r each phy device, controlled by a single atm device). in the case of a receive phy, the generation of the rx_c lav signal is independent of t he state machine. the rx_clav signal is asserted high at any time when a complete cell c an be received. thus as soon as the first byte of a cell is received, and ther e is no room for another cell in th e input fifo, the rx_cla v signal will be asserted low. in the case of a level-2 phy, the rx_clav?s will only be driven w hen the address was placed on the bus during the previous cycle. 4.5.3 errors on received cells if the mt90503 receiv es a short cell on any one of it s three ports, the cell will be di scarded, and a ne w cell will be started when the second soc signal is set. if the soc is not set after the 53rd byte of a receiv ed cell, subsequent bytes are ignored until a a new soc is received. data received on all of the three ports is examined for pa rity errors and an interrupt is raised if an error is found. cells are not discarded if a parity er ror is detected. register 0304h indicates on which port the parity error is detected. the atm hec is not examined on received cells.
mt90503 data sheet 81 zarlink semiconductor inc. 4.5.4 transmit and receive state machines for atm and phy modes figure 34 - atm mode state machines figure 35 - phy mode state machines idle (rx_enb=0) rx_clav=0 or rx_soc=0 rx_clav=1 and rx_soc=1 rx 1st byte rx next byte 53 bytes received rx_clav=1 <53 bytes and rx_clav=1 idle rx_clav=0 <53 bytes and rx_clav=0 rx_clav=1 rx_clav=0 discard cell rx_clav=1 and rx_soc=1 idle (rx_enb=1) no room for 1 cell room for 1 cell no room for 1 cell room for at least 1 cell idle cell not available or tx_clav=0 cell available and tx_clav=1 tx 1st byte (tx_soc=1, tx_enb=0) tx next byte (tx_soc=0, tx_enb=0) 53 bytes sent tx_clav=1 <53 bytes and tx_clav=1 idle tx_clav=0 <53 bytes and tx_clav=0 tx_clav=1 tx_clav=0 transmit state machine receive state machine idle (rx_clav=0) rx_enb=1** or rx_soc=0 rx_enb=0* and rx_soc=1 rx 1st byte rx next byte 53 bytes received rx_enb=0* <53 bytes and rx_enb=0* idle rx_enb=1** <53 bytes and rx_enb=1** rx_enb=0* rx_enb=1** discard cell rx_enb=0* and rx_soc=1 idle (rx_clav=1) no room for 1 cell room for 1 cell no room for 1 cell room for at least 1 cell * if mphy l2, add ?and rx_addr matches? ** if mphy l2, add ?or rx_addr doesn?t match? note: phy mode transmit and receive refers to the direction of cells as per the utopia specification. idle cell not available or tx_enb=1** cell available and tx_enb=0* tx 1st byte (tx_soc=1, tx_clav=1) tx next byte (tx_soc=0, tx_clav=1) 53 bytes sent tx_enb=0* <53 bytes and tx_enb=0* idle tx_enb=1** <53 bytes and tx_enb=1** tx_enb=0* tx_enb=1** transmit state machine receive state machine
mt90503 data sheet 82 zarlink semiconductor inc. 4.5.5 cell router cells are read on a round-robin basis from the four input fifos. cells from t he tx_sar that contain a ?0? in the msb of the txd field (see figure 36 on page 82) are written into the output fifos designated by the three lsbs of the txd field. cells from the tx_sar that contain a ?1? in the msb of the txd field and cells from the rxa, rxb, and rxc ports are handled based on the vpi/vci of the cell. the txd field for a cell is the same as the txd field in the tx_sar control struct ure that created the cell (see figure 29 on page 65). cells written into the rx_sar output fifo can be direct ed to the sar portion (cells to be formatted into tdm streams), to the data cell portion (to be examined by the cpu), or to both. this is indicated by the rxd field in cells written into the rx_sar output fifo. figure 36 - cell format for cells in inte rnal utopia input and output cell fifos gfc b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vpi vci[15:12] oam clp payload byte 44 txd rx structure pointer reserved gfc: generic flow control vpi: virtual path identifier vci: virtual circuit identifier oam: management cell. when this bit is set, the cell does not contain tdm bytes and is handled as an oam cell. pti: payload type indicator. clp: cell loss priority (this bit is not examined by the mt90503). payload byte x: payload byte in atm cell (48 bytes total, numbered 0 to 47). txd: tx_sar destination field. "0000" = discard cell "0xx1" = send to txa port "0x1x" = send to txb port "01xx" = send to txc port "1001" = treat as cell from rxa port "1010" = treat as cell from rxb port "1100" = treat as cell from rxc port others = reserved rxd: rx_sar destination field. "00" = reserved "x1" = data cell (write in rx data cell fifo in external control memory) "1x" = rx_sar cbr ce ll (disassemble this cell with structure pointed to by rx structure pointer (normal) field) rx structure pointer: pointer to the rx_sar structure that will be used to process the current cell. concatenated with "00000" to form a wp-bit address. (see rx_sar structure). note that rxa, rxb, and rxc input fifos do not contain any field beyond payload byte 47. also note that the tx_sar input fifo does not contain any field beyond txd. the txd field is not written in any of the output fifos note: the hec field of the atm cell is calculated and added for outgoing cells after the cell leaves the fifo. +0h +2h +4h +6h +30h +32h +34h +36h +38h +3ah +3ch +3eh payload byte 1 payload byte 3 payload byte 46 gfc payload byte 2 payload byte 0 payload byte 45 payload byte 47 pti rxd vci[11:0]
mt90503 data sheet 83 zarlink semiconductor inc. figure 37 - cell router flow 4.5.6 match & mask for cell routing cells are designated as "known" or "unknown" based on th e result of a match & mask (configurable for each port). for a cell to be considered "known" all vpi/vci bits whose corresponding mask bit is ?1? must have the value contained in the corresponding bit of the match regist er. the match and mask registers for port a are 0328h, 032ah, 032ch and 032eh. likewise the match and mask register for port b are 0342h, 0344h, 0348h and 034ah. for port c, the registers ar e 0368h, 036ah, 036ch and 036eh. figure 38 - match & mask example in addition, the cell router can be configured to elimin ate null cells (those with vpi = 0 and vci = 0). for the purpose of null cell elimination, the nni can be in cluded on a per-port basis (see registers 0300h and 0302h). replace vpi[7:0] in cell header replace vpi[11:8] in cell header incoming cell on utopia cell discarded vpi/vci match & mask (see section 4.5.6) oam cell no route using unknown non- oam cell routing no route using unknown oam cell routing yes ye s a a nni = ?1? vpi = ?1? vci = ?1? oam cell a, b = ?1? ye s no no no no no route cell according to ncr bits (see figure 39 on page 84) ye s ye s ye s ye s replcace vci[15:0] in cell header route according to ocr bits send a, b pulse to clock recovery vpi/vci = ?0? null cell elimination enabled null cell elimination disabled prior to cell router concatenate vpi/vci bits, read lut (see figure 40 on page 85) into 4-cell input fifo gfc | vpi | vci (from cell header) 0010 10000000 00000000 10110010 0000 00000000 00000000 10110010 0010 10000000 00000000 00000000 0000 00111111 00000000 11111111 0000 00000000 00000000 00000000 0010 10000000 00000000 10110 1 10 0000 00000000 00000000 10110 0 10 0010 10000000 00000000 00000 1 00 0000 00111111 00000000 11111 1 11 0000 00000000 00000000 00000 1 00 match value match result (1 = mismatch) mask value mask result (1 = mismatched cell) result routed according to lut entry routed as unknown cell for each bit, result = (match xor header) and mask
mt90503 data sheet 84 zarlink semiconductor inc. unknown non-oam cells and/or unknown oam cells can be discarded or directed to one or more output fifos. all unknown non-oam cells from a port ar e discarded or directed to the same location(s) and all unknown oam cells from a port are discarded or directed to the same location(s). unknown cells c an be directed differently for each port on which they were received. unknown cells cannot be sent to the sar portion of the rx_sar. the routing of unknown cells is set in registers 03a2h and 03a4h. known cells are handled according to the lut (look-up table) entry for the cell?s vpi/vci. 4.5.6.1 look-up tables entries lut entries direct cells with known vp i/vcis to either be discarded or plac ed in one or more of five possible destinations: the four output fifos and the data cell fifo in external control memory, by way of the rx_sar fifo. oam cells can be directed independently of non-oam cells wi th the same vpi/vci. oam cells cannot be directed to the sar portion of the rx_sar. lut entries can be either 4- or 8-bytes long (short or long lut entries, set in regi ster 302h). all look-up table entries in all three luts are the same size. 8-byte entries are only required if header translation is to be performed for one or more vcs. cells undergoing header translation have their nni bits, the remaining vpi bits and/or the vci bits replaced by the corresponding bits in the lut entry and are then either di scarded or sent to one or more of the possible destinations. vcs that undergo header translation are not directed to the sar portion of the rx_sar. clock recovery information can be gathered from up to tw o vcs by setting bit a in one lut entry and bit b in the same or another lut entry. a maximum of one vc can have bit a set and a maximum of one vc can have bit b set. figure 39 - short and long look-up table entries 4.5.6.2 lut addressing a lut base address exists for each of the three ports (registers 0320h, 0340h, 0360h). the lut base addresses for two or more ports can be the same. an identifier for a vc is created by concatenating any number of lsbs from the vpi and lsbs from the vci, to a maximum of 16 bits. the number of vci bits used is programmed in registers 0324h, 0344h and 0364h for port a, b, c respectively. the to tal number of bits in the identifier is programmed in registers 0322h, 0342h and 0362h for port a, b and c respec tively.the identifier is t hen appended with either two or three zeros (for either short or long lut entries). b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 reserved lut entry format for header translation non-header translation lut entry format nni: when ?1? the vpi[11:8] field in each cell for this lut entry will be replaced by the vpi[11:8] contained in this entry. vpi: when ?1? the vpi[7:0] field in each cell for this lut entry will be replaced by the vpi[7:0] contained in this entry. vci: when ?1? the vci[15:0] field in each cell for this lut entry will be replaced by the vci[15:0] contained in this entry. a, b: adaptive/srts clock recove ry vc a or vc b. only one vc can have bit a set. only one vc can have bit b set. ncr: normal (non-oam) cell routing ?00000? = discard ?xxxx1? = send to txa port ?xxx1x? = send to txb port ?xx1xx? = send to txc port ?x1xxx? = send to data cell fifo (in external control memory) via the rx_sar ?1xxxx? = send to sar portion of the rx_sar ocr: oam cell routing ?0000? = discard ?xxx1? = send to txa port ?xx1x? = send to txb port ?x1xx? = send to txc port ?1xxx? = send to data cell fifo (in external control memory) via the rx_sar note: if chip is configured for long lut entries, non-header translation lut entries are followed by two reserved words. ncr ocr 0 0 0 a b rx structure pointer nni vpi vci a b ncr ocr vci[15:12] vpi[11:8] vpi[7:0] vci[11:0]
mt90503 data sheet 85 zarlink semiconductor inc. finally, this value is used as the by te-pointer to the lut entry, offset from the lut base address for that port. figure 40 - vpi/vci concatenation and lut entry address example 4.5.6.3 utopia clocks each of the three ports must have a clock to operate t he receive interface and a clock to operate the transmit interface. two or more clocks may have the same source . these clocks can either be input to the mt90503 from an external source or output from the mt90503, from one of three internal utopia cloc ks. for each port the transmit clock and receive clock must be configured to be either both input or both output. an ex ception is port c where both transmit clock and receive clock must be input only. the source of the each of the three internal utopia cloc ks can be one of eight clocks: mclk, fast_clk, or any of the six utopia clocks (rxa, rxb, rxc, txa, txb, and txc). the sele cted clock is divided by n, an integer from 1 to 16, and can be inverted. other parts of the utopia module, including the look-up engine, the tx_ sar portion and the rx_sar portion operate off of mclk. 4.5.7 led operation the utopia module generates two led signals for port a (pins d2, h5) and two led signals for port b (pins w5, t5) in order to indicate the status of the a and b ports. the status conditions are: idle, presence of traffic, or phy alarm. when a port is in an idle state, both its leds are illuminated. if rx tr affic (other than null cells) is flowing, then the rx led for that port will flash; if tx traffic (other t han null cells) is flowing, t hen the tx led for that port will flash. if a phy alarm is detected, t he tx led is on and the rx led is off. the polarity of the led signals is active-low, i.e., a ?0? will turn the led on. the frequency of the leds is programmed in regist ers 0120h and 0122h while the leds are enabled in register 0302h. 0 0 0 0 lut base address (reg. 0320h) b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 notes: this example is for port a and for short lut entries. all three ports have independent parameters (vci_n, num_vpi_vci_bits, lut base address). identifier is a pointer, offset from the lut base address, to the first byte of the lut entry. identifier is appended with either "00" (short lut entries) or "000" (long lut entries). lut base address comprises bits 19:4 of the base address. "0000" is appended. lut entry address represents a byte address lut entry address vci vpi vci_na (reg. 0324h) = 5 vci bits concatenated vpi and vci b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . identifier b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b0 0 0 num_vci_vpi_bits (reg. 322h) = 16
mt90503 data sheet 86 zarlink semiconductor inc. figure 41 - utopia clock generation 4.5.8 utopia flow control the utopia module contains the ability to prevent cells in the 4-cell input fifos (r xa, rxb, rxc, and tx_sar) from being handled by the utopia module in the case that the 32-cell output fi fos (txa, txb, txc, and rx_sar) exceed programmable levels. an input fifo will be blocked when the level of any output fifo exceeds the level set for that combination of output fifo and input fifo. the levels can be set independently to 1 to 31 cells or to 0, which means no flow control will be exerted (see registers 0338h-033ah, 0358h-035ah, 0378h-037ah). ce ll arrival counters and cell departure counters for each port, stored in registers (0330h-0 336h, 0350h-0356h, 0370-0376h, 0390-0396h), are used to monitor the fill levels of each output fifo. 4.5.9 external interface signals due to the different possible configurat ions of the utopia ports, the functi ons of some pins change, depending on the configuration. some unused data pins when port a a nd/or port b are in 8-bit mode become general purpose inputs and/or outputs. when level-2 address ing is in place for port a, portions of the port b data buses are used for as port a addressing pins. the function of the clav (cell availabl e) and enb (enable data transfer) pins alternate when the port is in atm mode or phy mode (figure 42 on page 87). please note that the i/o direction of the pins remains the same. mclk fast_clk rxa_clk rxc_clk txa_clk txb_clk rxb_clk txc_clk divider by n (n=1 to 16) utopia_clk_1 inversion one of three utopia clock generators utopia_clk_1 utopia_clk_2 utopia_clk_3 rxa_clk one of six utopia clocks
mt90503 data sheet 87 zarlink semiconductor inc. figure 42 - external utopia interface 4.6 clock recovery module 4.6.1 overview the purpose of the clock recovery module is to sync hronise the tdm clock domain of the mt90503 with other devices on the network through information transmitted ac ross the atm link. clock recovery is necessary only when the mt90503 is operating as the tdm clock master. the clock recovery system is composed of several sub-components: 4.6.1.1 two point generation modules the point generation modules permit srts and/or adaptive clock recovery to be performed by the mt90503. the two modules provide the flexibility to have a back up clo ck recovery process operating from another vc and/or of the complementary type. these modules generate points wh ich are written to control memory and subsequently used by the clock recovery algorithm. 4.6.1.2 one srts (synchronous residual time stamp) generating module the srts generating module, is employed to generate the 4-bit outgoing rts value. 4.6.1.3 three integer divisor clock modules the integer divisor clock (idclk) modul es are designed to manipulate any incomi ng or internal clocks and produce an 8khz idclk. they provide the flexib ility of inverting the clo ck before or after division, option of setting the duty phy device mt90503 - atm mode txa_clk (h3) txa_soc (n2) txa_enb (h2) txa_clav (j5) txa_d (n4 . . .) txa_par (n3) txclk txenb txclav txsoc txdata txpar rxa_clk (c6) rxa_soc (h4) rxa_enb (b6) rxa_clav (a6) rxa_d (g3 . . .) rxa_par (g2) rxclk rxenb rxclav rxsoc rxdata rxpar mt90503 - phy mode txa_clk (h3) txa_soc (n2) txa_enb ( j5 ) txa_clav ( h2 ) txa_d (n4 . . .) txa_par (n3) rxclk rxenb rxclav rxsoc rxdata rxpar rxa_clk (c6) rxa_soc (h4) rxa_enb ( a6 ) rxa_clav ( b6 ) rxa_d (g3 . . .) rxa_par (g2) txclk txenb txclav txsoc txdata txpar atm device port a, phy mode port a, atm mode
mt90503 data sheet 88 zarlink semiconductor inc. cycle to 50%, 16-bit division and checking of the frequency (withi n a desired range). al ong with the idclk_loss signals, idclk?s are suited to being sent to an external pll. 4.6.1.4 two precise clock modules the precise clock (pclk) modules are used to divide mclk down to pclk_a and pclk_b. each module has a pclk_loss indicator which can be employed in tandem with the pclk sig nal to be routed to an extern al pll. the division of mclk is performed with a 16-bit integer and a 16-bit fraction, allowing for precise specification of the pclk frequency. these modules are ideally suited to being programmed by the clock recovery algorithm to generate the recovered clock. 4.6.1.5 eleven multiplexers the 11 multiplexers are: recov_a to recov_h, ct_netre f1, ct_netref2 and local_netref_16m. recov_a through recov_h and ct_netrefx are general i/o pins. local_netref_16m is an internal node, used as the master clock for the tdm section of the mt90503. 4.6.2 multiplexers there are eleven multiplexers (see table 28, ?source selection,? on page 89) with 36 possible inputs each (see table 29, ?idclk_a register,? on page 91): signal address bits recov_a 0860h 13:8 recov_b 0860h 5:0 recov_c 0862h 13:8 recov_d 0862h 5:0 recov_e 0864h 13:8 recov_f 0864h 5:0 recov_g 0866h 13:8 recov_h 0866h 5:0 ct_netref1 0868h 13:8 ct_netref2 0868h 5:0 local_netref_16m 086ah 5:0 table 27 - multiplexer registers
mt90503 data sheet 89 zarlink semiconductor inc. figure 43 - multiplexer source select number hex values source description 000000 0x00 logical 0 ground 000001 0x01 logical 1 vcc 000010 0x02 tri-state high-impedance 000011 0x03 reserved 000100 0x04 pclk_a precise clock 000101 0x05 pclk_valid_a precise clock valid 000110 0x06 pclk_b precise clock 000111 0x07 pclk_valid_b precise clock valid 001000 0x08 idclk_a integer divisor clock 001001 0x09 idclk_valid_a integer divisor clock valid 001010 0x0a idclk_b integer divisor clock 001011 0x0b idclk_valid_b integer divisor clock valid 001100 0x0c idclk_c integer divisor clock table 28 - source selection mclk pclk_a pclk_b pclk_valid_b idclk_a idclk_b pclk_valid_a idclk_c idclk_valid_a idclk_valid_b idclk_valid_c recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref1 ct_netref2 ct_c8_a ct_c8_b ct_c8 ct_frame_a ct_frame_b ct_frame ?0? ?1? output pins generated: recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref1 ct_netref2 local_netref_16m
mt90503 data sheet 90 zarlink semiconductor inc. 4.6.3 integer divisor clocks (idclk) there are three idclk modules in the mt90503. each module consists primarily of a 16-bit integer clock divider, but also has several clock manipulation circuits. these modules have the ability to flag an interrupt (if enabled - 0884h, 08a4h, 08c4h) if the input frequency is above or below a de sired range, invert the clock? s polarity (before and after division) and set the percentage duty cycle to 50%. idclk_lo ss_x signals the loss (or in correct frequency) of an input synchronisation clock, allowing the clock to easily be output to an external pll. idclk_a is configured in the register range of 0880h-0894h as described in table 29. 001101 0x0d idclk_valid_c integer divisor clock valid 001110 0x0e reserved 001111 0x0f reserved 010000 0x10 recov_a external i/o pin 010001 0x11 recov_b external i/o pin 010010 0x12 recov_c external i/o pin 010011 0x13 recov_d external i/o pin 010100 0x14 recov_e external i/o pin 010101 0x15 recov_f external i/o pin 010110 0x16 recov_g external i/o pin 010111 0x17 recov_h external i/o pin 011000 0x18 ct_c8 active clock: ct_c8_a or _b 011001 0x19 ct_c8_a tdm clock 011010 0x1a ct_c8_b tdm clock 011011 0x1b ct_frame active clock: ct_frame_a or _b 011100 0x1c ct_frame_a tdm clock 011101 0x1d ct_frame_b tdm clock 011110 0x1e ct_netref1 tdm clock 011111 0x1f ct_netref2 tdm clock 100000 0x20 ref_vca cell arrival on vc a 100001 0x21 ref_vcb cell arrival on vc b 100010 0x22 phy_alm_a phy alarm utopia a 100011 0x23 phy_alm_b phy alarm utopia b 100100 0x24 mclk master clock source select number hex values source description table 28 - source selection (continued)
mt90503 data sheet 91 zarlink semiconductor inc. these modules are ideally suited to dividi ng down the highly accurate reference clock (f n ) required when performing srts clock recovery. register bits name description 0880h [0] divisor_load_now set to load new value 0880h [1] divisor_reset 0 for reset, 1 for normal operation 0880h [2] even_duty_cycle_select when 1, 50% duty cycle is generated 0880h [3] input_invert_select invert clock before dividing 0880h [4] output_invert_select invert clock after dividing 0880h [13:8] input_source_select see table 28 0882h [5:0] status registers 0884h [5:0] interrupt enabling 0886h [5:0] manual setting of status registers 0888h [5:0] ext_loss_source_select external output of input clock status. see table 28. 0888h [6] ext_loss_source_polarity if set to ?1?, source loss is active high 0888h [7] output_loss_polarity if ?1? output loss is active high 088ah [15:0] clk_div denominator of clock divider 0890h [15:0] freqchck_div denominator of frequency check divider 0892h [15:0] freqchck_max_mclk_cycles max # of mclk?s between rising edges of the input clock divided by freqchck_div, if failure occurs, freq_too_low (0882h) will be set. 0894h [15:0] freqchck_min_mclk_cycles min # of mclk?s between rising edges of the input clock divided by freqchck_div, if failure occurs, freq_too_high (0882h) will be set. note: idclk_b and idclk_c have a corresponding set of registers in the ranges of 08a0h - 08b4h and 08c0h - 08d4h respectively. table 29 - idclk_a register
mt90503 data sheet 92 zarlink semiconductor inc. figure 44 - integer clock processor 4.6.4 precise clocks (pclk) the mt90503 has two digital pll (pclk) modules. using mclk as a source, the module will divide it with a 16-bit integer and optional 16-bit frac tion. the 16-bit fraction allows more prec ise specification on the output frequency. using the optional 16-bit fact ion in a typical configuration, mclk = 80mh z, pclk_int_a = 10 000 and pclk_a = 8khz, will increase the precision from 100 ppm to 1.5 ppm. also, using t he fractional divider will reduce the maximum jitter to one mclk period (12.5ns for 80mhz mclk). set pclk_frc to 0 if no jitter insertion by the pclk module desired. the divider can be programmed dynamically and has a maximum response time of 125 s. mclk ct_c8_a ct_c8_b ct_c8 ct_framea ct_frameb ct_frame recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref 50% duty cycle modifier 0880h[2] divider 088ah, 0880h[1:0] clock fre- quency checker 0890-0894h idclk_a idclk_valid_a 0880h [4] 0880h [3] 0880h [13:8] 50% duty cycle modifier 08a0h[2] divider 08aah, 08a0h[1:0] clock frequency checker 08b0-08b4h idclk_b idclk_valid_b 08a0h [4] 08a0h [3] 08a0h [13:8] 50% duty cycle modifier 08c0h[2] divider 08cah, 08c0h[1:0] clock frequency checker 08d0-08d4h idclk_c idclk_valid_c 08c0h [4] 08c0h [3] 08c0h [13:8] mclk ct_c8_a ct_c8_b ct_c8 ct_framea ct_frameb ct_frame recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref mclk ct_c8_a ct_c8_b ct_c8 ct_framea ct_frameb ct_frame recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h ct_netref 08a0h [2] 08c0h [2] 0880h [2]
mt90503 data sheet 93 zarlink semiconductor inc. the following registers are applicable: the following equation illust rates the derive d frequency of pclk from mclk: 4.6.5 point generation the function of the point generation module is to place points in external memory which have been generated by either the srts or adaptive clock re covery methods. these points express t he rates of the master device?s tdm clock (through a time stamp or the cell rate), the rate of the slave (performing the clock recovery) device?s master clock and the rate of the slave device?s pclk. this allows the clock recovery algorithm to evaluate the respective rates and make corrections to the pclk in or der to synchronise with the master device. there are two point generation modules. each can be conf igured for srts or adaptive clock recovery. the two modules each have a separate point generation process, separate timing reference and each is associated with one pclk module (i.e. pclk_a with adapsrts0 and pclk_b wi th adapsrts1). this allows switching between clock recovery types and/or sources on the fly. the a and b bits of the utopia look-up table determine which vc generates ref_vca and ref_vcb (s ee section 4.5.6.1 on page 84). register name description 0820h[5] adapsrts0_pclk_loss indicates state of clock 0820h[6] adapsrts0_pclk_divisor_load_now when set, pclk_div and pclk_frc are loaded into digital pll. 0820h[7] adapsrts0_pclk_divisor_reset when ?0? digital pll is in reset state 0830h adapsrts0_pclk_div integer divider of pclk_a 0832h adapsrts0_pclk_frc frac tional divider of pclk_a 0820h[5] adapsrts1_pclk_loss indicates state of clock 0840h[6] adapsrts1_pclk_divisor_load_now when set, pclk_div and pclk_frc are loaded into digital pll. 0840h[7] adapsrts1_pclk_divisor_reset when ?0? digital pll is in reset state 0850h adapsrts1_pclk_div integer divider of pclk_b 0852h adapsrts1_pclk_frc frac tional divider of pclk_b table 30 - pclk registers register bits name module 1 description 0820h 0 adaptive_enable a ?1? activates adaptive clock recovery 0820h 1 rx_srts_enable s ?1? activates srts clock recovery table 31 - adapsrts0 registers 2 f pclk f mclk pclk div pclk frc 65536 ----------------- + ----------------------------------------- - =
mt90503 data sheet 94 zarlink semiconductor inc. 0820h 2 ignore_crc b ?1? ignores crc of aal1 byte 0820h 3 ignore_parity b ?1? ignores parity bit of aal1 byte 0820h 4 ignore_seq_num b ?1? ignores sequence number of aal1 byte 0822h 0 aal1_crc_error b status bit indicating crc error 0822h 1 aal1_bad_parity b status bit indicating parity error 0822h 2 single_cell_lost b status bi t indicating single cell loss 0822h 3 multi_cell_lost b status bit indicating multiple cell loss 0822h 4 cell_misinserted b status bit i ndicating a cell misinsertion error 0822h 5 timeout_flag b status bit indicating interval since last cell exceeds time_out_period (0828h) (reset when timeout ceases) 0822h 6 timeout_pulse b status bit indica ting the interval between two cells has exceeded the time_out_period (0828h) 0822h 7 rx_srts_remote_overflow s status bit indicating the interval between remote srts values received was too short and one was lost 0822h 8 rx_srts_local_overflow s status bit indicating the interval between local srts values received was too short and one was lost 0824h [8:0] interrupt enables 0826h [5:0] ref_input_select a timing referenc e (usually ref_vca or ref_vcb), see table 28. 0826h [13:8] rx_fnxi_input_select s se lects fnxi input, see table 28. 0828h [15:0] time_out_period b time-out peri od between two cells (units - 1024 mclk cycles) 082ah [7:0] adap_pnt_elim_x a "keep 1 point out of x" and write to external memory 082ch [15:0] srts8m8c_div_p s pclk must be divided by k in order to match the interval of 8 srts carrying cells, where k = p/q, p is normally the number of frames in the scheduler, i.e. 375 for fully filled structured aal1 082eh [15:0] srts8m8c_div_q s q is the number of channels open 1. adaptive relevant register, s - srts relevant register, b - relevant to both 2. a corresponding set of registers exists for adapsrts1 from 0840h - 084eh. register bits name module 1 description table 31 - adapsrts0 registers 2 (continued)
mt90503 data sheet 95 zarlink semiconductor inc. figure 45 - adaptive clock recovery 4.6.6 adaptive clock recovery adaptive clock recovery is a method which generates a clock based on the rate at which aal1 cells are arriving. the device acting as the master does not have to structure its cells differen tly or add any information, it simply transmits cbr data in aal1 cells. the slave device performs the adaptive clock recovery, based on a clock recovery algorithm using points placed in ex ternal memory by the point generation module. to perform adaptive clock recovery, t he point generation module of the mt90503 is normally configured with the cell arrival event (ref_vca or ref_vcb) as its timing re ference (source 0x20 or 0x21 of table 28, ?source selection,? on page 89). the vc?s which are defined as vca and vcb are recorded in the utopia lut (see figure 39 on page 84). the input multiplexer gives the flexibility to us e any clock desired. the cell arrival event is received directly from the utopia look-up module. the look-up engine generates a vc-specific pulse and passes on the aal1 byte of the received cell. the aal1 byte is composed of a sequence number (sn), crc-3 sequence number protection (snp) and a parity bit. the adaptive module checks for crc and parity erro rs. if errors are found, the cell is ignored and the appropriate bit of register 0822h or 0842h is flagged. the sequence number is also verified to determine if cells have been lost. single cell losses can be compensated for and the single_cell_lost regist er bit (0822h or 0842h [2]) will be set. multiple cell lo sses cannot be compensated, but will be flagge d as either mu lti_cell_l ost (0822h or 0842h [3]) or cell_misinserted (0822h or 0842h [4]). elimination of cells with bad crc or parity, compensation for lost cells cell counter point generation process lost_cell_pulse valid_cell_pulse point elimination (keeps 1 point out of x cells) cell_counter [31:0] ref_input_select pclk_div pclk_frc load_divisor_now precise clock generator pclk counter mclk counter pclk pclk_integer[31:0] pclk_fraction[15:0] mclk_counter[31:0] write points to external control memory time-out detection ref_vca ref_vcb aal1 byte from registers
mt90503 data sheet 96 zarlink semiconductor inc. figure 46 - adaptive cell reception flow the point recording portion of the modul e records three fields. the ?number of the cell? is a 32-bi t field, the ?number of mclk cycles? counted at time of cell arrival is a 32-bi t field and the ?number of pclk cycles? counted when the cell received is a 48-bit field composed of a 32-bit integer and 16-bit fr action. this information, from the three counters (cell, mclk and pclk), 112 bits in total, is written to exte rnal control memory in a circular buffer reserved for clock recovery information. (see external memory point format on page 98.) ratios of this data are compared by the clock recovery algorithm to the desired ratios and co rrespondingly, corrections are made to the pclk frequency dividers. it is possible to eliminate some of the timing reference ce lls sent to memory. this may be done in order to conserve processing power. it is especially useful if the clock reco very vc has a high number of channels (i.e. a high rate of cell arrival). the 8-bit registers, adap_pnt_elim_x (082a h and 084ah) can be programmed to "keep one point out of x". each adaptive module has its own associated pclk generat or, allowing the wander of each vc to be tracked with respect to the pclk frequency. 4.6.6.1 srts clock recovery the synchronous residual time stamp (srts) method of clock recovery is standardised in itu-t i.363.1, ansi t1.630 and bellcore?s patent 1 (u.s. patent 5 260 978 (11/93)). the srts method uses a stream of residual time st amps (rts) to express the difference between a common reference clock (f n ) and a local service clock (f s - derived from the local tdm clock, ct_c8_x). 1. zarlink has entered into an agreement with bellcore with respect to bellcore?s u.s. patent no. 5,260,978 and zarlink?s manu facture and sale of products containing the srts function. however the purchase of this product does not grant the purchaser any rights under u. s. patent no. 5,260,978. use of this product or its resale as a component of another product may require a license under the patent which is available from bell communications research, inc., 445 south street, morristown, new jersey 07960. parity ok and crc ok aal1 byte discard cell sn = last sn + 1 sn = last sn + 2 sn = last sn - 1 & last sn = seclast sn + 2 generate ?ref_vcx? pulse discard cell (multiple cell loss detected) generate two ?ref_vcx? pulses (lost cell detected) discard cell (misinserted cell detected) no no no no yes ye s ye s yes
mt90503 data sheet 97 zarlink semiconductor inc. the point generation modules can both be configured for sr ts clock recovery and receive data simultaneously from 2 vcs. like adaptive clock recovery, the data is re trieved from the utopia look -up module. the srts values however, are spread over 8 cells. as in the adaptive mode , crc errors, parity errors and missing cells are reported to their respective registers (0822h & 0842h [4:0]). this component of the srts recovery that receives srts data on a vc from an outside source generates "remote" data the srts clock recovery method requires an accurate external reference clock (f n ) (e.g., a stratum 3 clock). this clock drives the 4-bit counter fnxi_cnt. this count is compared to a count driv en by the precise clock digital pll. in order to match the interval of 8 srts carrying cells, pclk (8 khz) must be multiplied by k. k is proportional to the number of frames in the scheduler (p ) (375 for fully filled stru ctured aal1) and inversely proportional to the number of channels open (q) (respectively of registers 082ch and 082eh for point generation module 0 (adapsrts0)). i.e., k=p/q. this component of the srts clock recovery that compares the pclk generated cl ock with that of the fnxi clock generates "local" data. these "local" and "remote" values are written to external memory for the cpu to access. figure 47 - rx srts clock recovery module 4.6.7 srts transmission similar to the srts receive side, the generation of srts data must take into account the number of frames in the scheduler (p of register 0818h) and t he number of channels in the vc (q of register 081ah). a single vc may be used to carry srts or the srts values may be broadcast on multiple vcs. these vcs must, however, be of the same format, consistent with the master srts vc. t hese vc?s are configured in the tx sar (see table 22 on page 65). input* 1024 pclk 8 cell pulse input/ ((p * 1024) / q) to external control memory 8.192 mhz rx srts value writter (to external memory) recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h idclk_a idclk_b idclk_c fnxi fnxi_cnt[3:0] ref_vcx aal1 byte elimination of cells that have bad crc/parity srts value concatenation lost and misinserted cell compensation rx srts value writter (to external memory) time-out detection local remote write_now srts_value[3:0] bad_srts_value to external control memory
mt90503 data sheet 98 zarlink semiconductor inc. figure 48 - tx srts clock recovery module 4.6.8 external memory point format figure 49 on page 99 indicates the form at of the circular buffers in exte rnal memory that contain srts and adaptive point information. in adaptive cl ock recovery, a point is the information pertinent to the reception of a single cell. in srts, a point is the information corresponding to reception of an srts value (gathered over eight cells). if the received srts value is corrupt (due to errors in the received cells) the valid bit (v) will be 0. register bits name description 0810h 0 enable ?1? enables tx srts 0810h [1:2] bus_clk_sel source of timing: ?10? - ct_c8_a,?11? - ct_c8_b,?0x? - follows active clock, ct_c8_a or _b 0810h [8:13] fnxi_input_select selects source of fnxi see table 28 0812h 0 overflow set if values sent by tx srts is greater than the number of values read by the tx sar 0812h 1 underflow set if the number of tx srts values is less than that read by the tx sar 0814h [0:1] interrupt enables 0818h [0:15] srts8m8c_div_p p = numbe r of frames in the scheduler 081ah [0:15] srts8m8c_div_q q = number of channels open table 32 - tx srts registers recov_a recov_b recov_c recov_d recov_e recov_f recov_g recov_h idclk_a idclk_b idclk_c input/ ((p * 1024) / q) ct_c8_a ct_c8_b ct_c8 5 value srts buffer fnxi_cnt[3:0] change srts to txsar fnxi 8 cell pulse
mt90503 data sheet 99 zarlink semiconductor inc. figure 49 - clock recovery information buffers field name of field bits used description v valid bit b12 set if the accompanying rx srts value is valid rx srts remote srts value b11:b8 the 4-bit srts value from the incoming atm cells on the designated vc. local srts local srts value b3:b0 the 4-bit srts value calculated based on pclk and fnxi table 33 - srts pointer buffer, field description rx srts local srts v rx srts local srts v rx srts local srts v b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 rx srts local srts v b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 pclk counter integer [31:16] pclk counter integer [15:0] pclk counter fraction [15:0] mclk counter [31:16] mclk counter [15:0] cell counter [31:16] cell counter [15:0] +0 +2 +4 +6 +8 +a +c +e point 0 point 1 point 2 point 3 point n point 4 +0 +10 +20 +30 +40 reserved adaptive point buffer note: the base address and size of each buffer is configurable in registers 090eh - 0912h, 091ch - 0920h.
mt90503 data sheet 100 zarlink semiconductor inc. 5.0 memory 5.1 memory overview the mt90503 requires external memory for two purposes: control and data memory. the control memory contains information required for: tx_sars and rx_sars control structures, transmission schedu lers, look up values to map vcs to rx structures. the control memory also stor es data cell fifo?s. cas buffers and clock recovery data is also stored in the control memory. the data memory is employed to store network traffic data for a maximum of 2048 bi-directional tdm channels. the mt90503 interfaces with the external data ssram via the following pins: 19 address pins (dmem_a), 4 memory bank/chip selection pins (dmem_cs), 16 data pins , (dmem_d), 2 parity pins (dmem_par), 1 r/w(low) pin used for late write memories (dmem_rw), 2 data memory byte write select pins (dmem_bws) and a memory clock (mem_clk). the external control ssrams interface pins: 19 address pins (cmem_a), cmem_a[18] can be configured as a: memory bank/chip selection pin (c mem_cs[1]) or an address pin cmem_a[18], 1 dedicated memory bank/chip selection pin (cme m_cs[0]), 16 data pins, (cmem_d), 1 r/w(low) pin used for late write memories (cmem_rw), 2 control memory byte write select pins (cmem_bws). the data memory supports up to 4 memory banks up to 512 k words per bank determining a data memory limit of 4 mb. the data memory clock speed gamut is 40 mhz to 80 mhz. note: recommended mem_clk speed is 80 mhz. the option of a reduced memory capability is also supported. the following ssram sizes can be employed: 128 kb, 256 kb, 512 kb and 1 mb. the data bus consists of 18 data bits where two data bits are dedicated as parity bits. the parity bits are used to detect underruns in the circular buffers generated on the atm link and data error detection. the parity check can be disabled to permit n on-parity memory compatibility. the mt90503 supports 1, 2, 3 or 4 banks of external memory, each bank having a total ca pacity ranging from 64 k x 18 bits to 512 k x 18 bits. therefore the mt90503 can operate with external memory ranging from 128 kb to 4 mb. the above data memory configuration is initialised via: data memory parity 0 register, data memory parity 1 register and data memory configuration register (0248h, 024ah & 024ch respectively). the control memory maximum capacity is 512 k words and supports 2 memory banks. the reduced memory capability is supported in the same manner as the data memory. however, if all 19 address bits are employed then the use of 1 memory bank is permitt ed. therefore the mt90503 can operate wi th external control memory ranging from 128 kb to 1 mb. the mt90503 dose not use the parity bits supplied by the control memory. parity bits can be generated within the mt90503 and are used for error dete ction. the above control memory configuration is initialised via: control memory pa rity 0 register, control memory pa rity 1 register and control memory configuration register (0240h, 0242h & 0244h respectively). the mt90503 supports both pipelined and flow through ssram employing either: ?normal? or ?zero bus turnaround? (zbt) operation. when pecl clock is employ ed ?late-write? is suppo rted in ?normal? operation. the memory clock (mem_clk) interface must be configured to either pecl or ttl. the interface can be initialised via the ?cpu control register? address 0100h. the external memory controller can interface with several types of ssram, but they must support synchronous bus enabling. the ssram chip must only enable its data out put buffers one cycle after a read (two for pipelined ssram), irrespective of the state of the asynchronous ou tput enable pin. a read is indicated by mem_rw high and the appropriate mem_cs asserted. the ssram can be a registered input type (syn chronous, synchronous flow through or synchronous burst) or a registered input/output type (synch ronous pipelined). although the mt90503 uses synchronous access feature of the memory, it does not use the burst access feature of the memory. specific synchronous sram devices may require a turnaround cycle with respect to the bidirectional data bus. the mt90503 can be configured to insert a turnaround cycle between read ac cess and write access. a turnaround cycle can be inserted between read access and read access to other memory banks. the turnaround cycle configuration is initialised via: cont rol memory configuration register and data memory configuration register (0244h & 024ch respectively). it should be noted that turnaround cycles restrict the memory bandwidth and therefore the operation mt90503. maxi mum throughput is achieved with full clock speed on mclk and without pipelined synchronous ram and turnaround cycles.
mt90503 data sheet 101 zarlink semiconductor inc. 5.2 memory map the location of the absolute starting and ending addresses of the internal and external memories are shown in table 34 - mt90503 memory map. the complete set of inter nal registers is listed in section 5.5 "detailed register description", on page 99. table 34 - mt90503 memory map 5.3 memory controllers two memory controllers for external ssram exist in the mt90503: one for data memory and one for control memory. the memory controller blocks of the mt9050 3 reside between the internal blocks and the external memory. they receive memory access requests from the internal blocks (tdm, tx_sar, rx_sar, and cpu interface modules) and service them by reading data from, or writing data to, the external memories. 5.3.1 data memory the data memory contains ? tx/rx circular buffers: one per channel, each with a programmable size of 128, 256, 512, or 1024 words. start address end address name 0100h 01feh cpu registers 0200h 02feh main registers 0300h 03feh utopia registers 0400h 04feh tdm registers 0500h 05feh tx_sar registers 0600h 06feh scheduler registers 0700h 07feh rx_sar registers 0800h 08feh clock registers 0900h 09feh miscellaneous registers 0a00h 0afeh h.100 registers 1000h 10feh tx sar input fifo 1400h 14feh utopia port a input fifo 1800h 18feh utopia port b input fifo 1c00h 1cfeh utopia port c input fifo 2000h 27feh rx sar output fifo 3000h 33feh utopia port a output fifo 4000h 43feh utopia port b output fifo 5000h 53feh utopia port c output fifo 8000h bffeh tdm channel association memory 200000h 2ffffeh external control memory 400000h 7ffffeh external data memory
mt90503 data sheet 102 zarlink semiconductor inc. the data memory can be up to 4 mb in size. this allo ws 2048 tdm channels to each have a maximum-size circular buffer: 2048 tdm channels * 2048 bytes/channel = 4 mb. a pari ty bit, necessary to detect underruns on incoming tdm data, can be disabled, allowing non-parity memory to be used. the parity bit, when enabled, is also used for error detection. the data memory can be distributed betw een one and four banks. 16 to 19 address bits are required to access the 128 kb to 1 mb banks of data memory. 5.3.2 control memory the control memory contains ? tx control structures: one per vc, minimum of 12 words each, maximum of 48 kb total ? rx control structures: one per vc, minimum of 14 words each, maximum of 56 kb total ? transmit event schedulers: up to fifteen, ty pical sizes are 6 to 150 kb per enabled scheduler ? look-up table: three luts, each with one entry per known vc, 4 or 8 bytes per entry ? data cell fifo: two fifos, each programmable in length from 4 to 16384 cells, 32 words per cell ? cas change buffers: 1 to 32768 words in size ? silent tone buffers: 1 to 32768 words in size ? clock recovery point buffers: 9216 words in size ? error message buffer: programmable length of 0 to 65536 error report structures, 4 words per structure. the control memory can be up to 1 mb in size. a parity bit is used for error detection. the control memory can be distributed in either one or two banks. as with the data memory, 16 to 19 address bits are employed; when 19 address bits are used, only one memory bank can be supported. 5.3.3 data memory controller there are five agents which interact with the data me mory controller: tx_sar, rx_sar, tdm transmit, tdm receive, and cpu (through the cpu interface). of these fi ve agents, all but the cpu send their accesses to their internal cache, one for each agent, from which the data is written into the data memory when the data memory bus is available. the internal caches are capable of buffering up to 128 words each. the cpu has the highest priority on the write accesses an d writes whenever it is flagged to do so. the priority arbitration used for accesses to the cpu is described in more detail the cpu module section (see 4.1 on page 34). the memory controller generates the crc-32 needed for each aal5-vtoa cell. agent access types tx_sar reads rx_sar writes tdm transmit writes tdm receive reads cpu reads and writes table 35 - types of data memory accesses for each agent
mt90503 data sheet 103 zarlink semiconductor inc. 5.3.4 control memory controller unlike the data memory controller, the control memory controller does not contain internal caches. agents? read/write requests are granted on a cycle-by-cycle basis and each agent waits until its request has been completed. each agent has its own access port allowi ng it to communicate address, data, r/w, and write enable information with the memory controller. the agents are identified in table 36 - on page 103. arbitration between the agents for control memory access is as follows: an agent can request a read or write at any time. the control memory will continue in its current mode (read or write) until no requests of that type are pending. then, it will switch and service requests of the other mode. the cpu has the highest priority if the memory controller is handling accesses of the mode that the cpu requests. other agents are granted access on a first-come first-served basis if the memory contro ller is handling accesses of the mode the agent requests. 5.4 register overview this section describes the mt90503's internal registers. an 8 kb memory block is reserved for the register mapping. the register descriptions are gr ouped in the following sections: ? cpu module interface ? main registers ? utopia module ? tdm module ? tx_sar module ? rx_sar module ? clock registers ? miscellaneous registers ? h.100/h.110 bus registers agent access types tx_sar reads and writes rx_sar reads and writes utopia (lut) reads and writes cpu reads and writes table 36 - types of control memory accesses for each agent
mt90503 data sheet 104 zarlink semiconductor inc. 5.5 detailed register description 5.5.1 cpu registers address: 100h label: control reset value: 0000h label bit position type description nreset_registers 0 rw controls the reset for the mainreg module and certain cpu functions. '1' out of reset. '0' in reset. should not be removed unless mclk is present. nreset_chip_mclk_src 1 rw resets all other parts of the chip. '1' out of reset. '0' in reset. should not be removed unless mclk is present. nreset_txa_clk_mclk_src 2 rw nreset for utopia txa clock (syncronized on mclk_src). this reset should not be removed unless the corresponding clock is present. nreset_txb_clk_mclk_src 3 rw nreset for utopia txb clock (syncronized on mclk_src). this reset should not be removed unless the corresponding clock is present. nreset_txc_clk_mclk_src 4 rw nreset for utopia txc clock (syncronized on mclk_src). this reset should not be removed unless the corresponding clock is present. nreset_rxa_clk_mclk_src 5 rw nreset for utopia rxa clock (syncronized on mclk_src). this reset should not be removed unless the corresponding clock is present. nreset_rxb_clk_mclk_src 6 rw nreset for utopia rxb clock (syncronized on mclk_src). this reset should not be removed unless the corresponding clock is present. nreset_rxc_clk_mclk_src 7 rw nreset for utopia rxc clock (syncronized on mclk_src). this reset should not be removed unless the corresponding clock is present. reserved 8 rw for future use: reserved for mem_clk oe (ttl) reserved 9 rw for future use: reserved for pecl oe mem_clk_o_enable 10 rw enables the mem_clk ttl output to toggle, active high mem_clk_pecl_enable 11 rw enables the mem_clk pecl output to toggle, active high mem_clk_input_sel 12 rw '0' = mem_clk_i pin, '1' = mem_clk pecl pins write_cache_enable 13 rw when '0', only 1 access can be treated at a time. when '1', write cache contains 128 accesses. if this bit is '1', the average latency to perform a write will be reduced, but the worst-case latency will be increased. reserved 14 rw reserved. must be set t o "0". test_status 15 ts when '1', all the status bits in the register will be set. table 37 - cpu control register
mt90503 data sheet 105 zarlink semiconductor inc. address: 102h label: status0 reset value: 0000h label bit position type description reserved 0 ro reserved. always read as "0". reserved 1 ro reserved. always read as "0". reserved 2 ro reserved. always read as "0". internal_read_timeout 3 rol goes high if a read access has been active for 32k mclk_src cycles without completi on. fatal chip error. inmo_read_done 4 rol indicates that an extended indi rect access has completed. this is used to indicate to the host that read data is ready. reserved 15:5 rol reserved. always read as "0000_0000_000" table 38 - cpu status register address: 104h label: status0_ie reset value: 0000h label bit position type description reserved 0 ro reserved. always read as "0". reserved 1 ro reserved. always read as "0". reserved 2 ro reserved. always read as "0". internal_read_timeout_ie 3 ie when '1' and t he corresponding status bit is '1', an interrupt will be generated. inmo_read_done_ie 4 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. reserved 15:5 ro reserved. always read as "0000_0000_000". table 39 - cpu interrupt enable register address: 10eh label: counters reset value: 0000h label bit position type description emul_mode 1:0 emo indicates state of counters and status bits. "00" = normal mode, "01" = reset, "1x" = test mode. these bits are only present for tests and should never be used. reserved 15:2 rw reserved. must be "0000_0000_0000_00" table 40 - cpu counter register
mt90503 data sheet 106 zarlink semiconductor inc. address: 120h label: led1 reset value: 3fd0h label bit position type description mclk_src_freq[6:0] 6:0 rw mclk_src frequency in mhz led_flash_freq[8:0] 15:7 rw determines the time in ms that the leds will be turned off to indicate link activity. table 41 - led1 register address: 122h label: led2 reset value: 0000h label bit position type description led_test_mode 0 rw if '0', the led flashing time will be determined in ms. if '1', the led flashing time will be determined in us. reserved 15:1 rw reserved. must be "0000_0000_0000_000" table 42 - led2 register address: 128h label: pll_conf reset value: 00a1h label bit position type description pll_div_x 2:0 rw divides mclk_src before ent ering the ref pin of the fast_clk pll. together, pll_div_x and pll_div_y determine the speed of fast_clk, which must be between 160 and 200 mhz. pll_div_y 5:3 rw divides the feedback path from the output pin of the fast_clk pll. together, pll_div_x and pll_div_y determine the speed of fast_clk, which must be between 160 and 200 mhz. pll_div_z 10:6 rw divides fast_clk to generate mem_clk pll_bypass 11 rw if '1', mclk_src divided by pll_div_x becomes fast_clk, bypassing the fast_clk pll nreset_pll_async 12 rw resets the module that di vides mclk_src before being used as the ref pin of the fast_clk pll reserved 15:13 ro reserved. always read as "000" table 43 - pll configuration register
mt90503 data sheet 107 zarlink semiconductor inc. address: 130h label: inmo_a_gpi0 reset value: 0000h label bit position type description inmo_a_in[14:0] 14:0 ro current level of the corresponding pin reserved 15 ro reserved. always read as "0" table 44 - intel/motorola address register address: 132h label: inmo_a_gpi1 reset value: 0000h label bit position type description inmo_a_rise0 0 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise1 1 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise2 2 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise3 3 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise4 4 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise5 5 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise6 6 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise7 7 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise8 8 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise9 9 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise10 10 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise11 11 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise12 12 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise13 13 rol this bit is set if the correspon ding pin goes for '0' to '1' inmo_a_rise14 14 rol this bit is set if the correspon ding pin goes for '0' to '1' reserved 15 ro reserved. always read as "0:" table 45 - intel/motorola address rise register
mt90503 data sheet 108 zarlink semiconductor inc. address: 136h label: inmo_a_gpi2 reset value: 0000h label bit position type description inmo_a_fall0 0 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall1 1 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall2 2 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall3 3 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall4 4 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall5 5 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall6 6 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall7 7 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall8 8 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall9 9 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall10 10 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall11 11 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall12 12 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall13 13 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_a_fall14 14 rol this bit is set if the corresponding pin goes for '1' to '0' reserved 15 ro reserved. always read as "0" table 46 - intel/motorla address fall register address: 140h label: inmo_d_gpo reset value: 0000h label bit position type description inmo_d_out8 0 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit inmo_d_out9 1 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit inmo_d_out10 2 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit inmo_d_out11 3 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit table 47 - intel/motorola data out register
mt90503 data sheet 109 zarlink semiconductor inc. inmo_d_out12 4 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit inmo_d_out13 5 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit inmo_d_out14 6 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit inmo_d_out15 7 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit inmo_d_oe8 8 rw this is oe bit used to drive the corresponding pin. inmo_d_oe9 9 rw this is oe bit used to drive the corresponding pin. inmo_d_oe10 10 rw this is oe bit used to drive the corresponding pin. inmo_d_oe11 11 rw this is oe bit used to drive the corresponding pin. inmo_d_oe12 12 rw this is oe bit used to drive the corresponding pin. inmo_d_oe13 13 rw this is oe bit used to drive the corresponding pin. inmo_d_oe14 14 rw this is oe bit used to drive the corresponding pin. inmo_d_oe15 15 rw this is oe bit used to drive the corresponding pin. address 142h: label: inmo_d_gpi0 reset value: 0000h label bit position type description inmo_d_in8 0 ro current level of the corresponding pin inmo_d_in9 1 ro current level of the corresponding pin inmo_d_in10 2 ro current level of the corresponding pin inmo_d_in11 3 ro current level of the corresponding pin inmo_d_in12 4 ro current level of the corresponding pin inmo_d_in13 5 ro current level of the corresponding pin inmo_d_in14 6 ro current level of the corresponding pin inmo_d_in15 7 ro current level of the corresponding pin reserved 15:8 ro reserved. always read as "0000_0000" table 48 - intel/motorola data in register address: 140h label: inmo_d_gpo reset value: 0000h label bit position type description table 47 - intel/motorola data out register (continued)
mt90503 data sheet 110 zarlink semiconductor inc. 5.5.2 main registers address 144h: label: inmo_d_gpi1 reset value: 0000h label bit position type description inmo_d_rise8 0 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_rise9 1 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_rise10 2 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_rise11 3 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_rise12 4 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_rise13 5 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_rise14 6 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_rise15 7 rol this bit is set if the corresponding pin goes for '0' to '1' inmo_d_fall8 8 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_d_fall9 9 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_d_fall10 10 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_d_fall11 11 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_d_fall12 12 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_d_fall13 13 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_d_fall14 14 rol this bit is set if the corresponding pin goes for '1' to '0' inmo_d_fall15 15 rol this bit is set if the corresponding pin goes for '1' to '0' table 49 - intel/motorola data rise/fall register address: 200h label: control reset value: 0000h label bit position type description reserved 14:0 ro reserved. always read as "0000_0000_0000_000" test_status 15 ts when '1', all the status bits in the register will be set. table 50 - main control register
mt90503 data sheet 111 zarlink semiconductor inc. address: 202h label: status0 reset value: 0000h label bit position type description cmem_parity_error0 0 rol indicates a parity error on data received from the control memory on the data bits [7:0]. this will only be detected if cmem_parity_conf[0] is '0'. cmem_parity_error1 1 rol indicates a parity error on data received from the control memory on the data bits [15:8]. this will only be detected if cmem_parity_conf[1] is '0'. dmem_parity_error0 2 rol indicates a parity error on data received from the data memory on the data bits [7:0]. this will only be detected if dmem_parity_conf[0] is '0'. dmem_parity_error1 3 rol indicates a parity error on data received from the data memory on the data bits [15:8]. this will only be detected if dmem_parity_conf[1] is '0'. reserved 15:4 rw reserved. must be "0000_0000_0000" table 51 - main status register address: 204h label: status0_ie reset value: 0000h label bit position type description cmem_parity_error0_ie 0 ie when '1' and t he corresponding status bit is '1', an interrupt will be generated. cmem_parity_error1_ie 1 ie when '1' and t he corresponding status bit is '1', an interrupt will be generated. dmem_parity_error0_ie 2 ie when '1' and t he corresponding status bit is '1', an interrupt will be generated. dmem_parity_error1_ie 3 ie when '1' and t he corresponding status bit is '1', an interrupt will be generated. reserved 15:4 rw reserved. must be "0000_0000_0000" table 52 - main interrupt enable register
mt90503 data sheet 112 zarlink semiconductor inc. address: counters label: 20eh reset value: 0000h label bit position type description emul_mode 1:0 emo indicates state of counters and status bits. "00" = normal mode, "01" = reset, "1x" = test mode. these bits are only present for tests and should never be used. reserved 15:2 rw reserved. must be "0000_0000_0000_00" table 53 - main counter register address: 220h label: interrupt_flags reset value: 0000h label bit position type description cpureg_interrupt_active 0 ro when '1', indicates that the interrupt request for this module is active. mainreg_interrupt_active 1 ro when '1', indicates that the interrupt request for this module is active. utoreg_interrupt_active 2 ro when '1', indicates that the interrupt request for this module is active. txreg_interrupt_active 3 ro when '1', indicates that the interrupt request for this module is active. rxreg_interrupt_active 4 ro when '1', indicates that the interrupt request for this module is active. miscreg_interrupt_active 5 ro when '1', indicates that the interrupt request for this module is active. wheelreg_interrupt_active 6 ro when '1', indicates that the interrupt request for this module is active. clkreg_interrupt_active 7 ro when '1', indicates that the interrupt request for this module is active. tdmreg_interrupt_active 8 ro when '1', indicates that the interrupt request for this module is active. mastreg_interrupt_active 9 ro when '1', indicates that the interrupt request for this module is active. table 54 - interrupt flags register
mt90503 data sheet 113 zarlink semiconductor inc. casalarm_interrupt_active 10 ro the cas alarm occurs after the cas alarm timeout period or if the cas buffer becomes half full. this is used to ensure that the host can empty the cas change buffer in a timely manner without having to poll its fill continuously. tdmalarm_interrupt_active 11 ro when ?0?, the clock divisor module is held in reset. clkrecovalarm_interrupt_active 12 ro the clock recovery alarm occurs after the clock recovery alarm timeout period or if ei ther clock recovery buffer becomes half full. this is used to ensure that the host can empty the clock recovery point buffers in a timely manner without having to poll its fill continuously. aal0alarm_interrupt_active 13 ro the aal0 alarm occurs after the aal0 alarm timeout period or if the aal0 buffer becomes half full. this is used to ensure that the host can empty the aal0 cell buffer in a timely manner without having to poll its fill continuously. erroralarm_interrupt_active 14 ro the error alarm occurs after the error alarm timeout period or if the error report structure buffer becomes half full. this is used to ensure that the host can empty the error structure buffer in a timely manner without having to poll its fill continuously. interrupt1_treated 15 pul software must write this bit to ?1?, when it has finished servicing interrupts. address: 224h label: interrupt1_conf reset value: 0000h label bit position type description min_interrupt1_period 13:0 rw number of us between interrupts (minimum). when 0000h, these is no minimum interval between interrupts. programming this prevents the host from being flooded with interrupts. each interrupt will last 1 us. interrupt1_polarity 15:14 rw interrupt polarity and output enable. "00"=active low (open-collector); "01"=active high (open-collector); "10" = drive low; "11" = drive high. drive low or drive high means that the pin's value will not change regardless of internal interrupts. table 55 - interrupt1 configuration register address: 220h label: interrupt_flags reset value: 0000h label bit position type description table 54 - interrupt flags register (continued)
mt90503 data sheet 114 zarlink semiconductor inc. address: 226h label: interrupt2_conf reset value: 0000h label bit position type description reserved 13:0 rw reserved. must be "0000_0000_0000_00" interrupt2_polarity 15:14 rw interrupt polarity and output enable. "00"=active low (open-collector); "01"=active hi gh (open-collector); "10" = drive low; "11" = drive high. drive low or drive high means that the pin's value will not change regardless of internal interrupts. table 56 - interrupt2 configuration register address: 228h label: interrupt1_enable reset value: 0000h label bit position type description cpureg_interrupt1_enable 0 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. mainreg_interrupt1_enable 1 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. utoreg_interrupt1_enable 2 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. txreg_interrupt1_enable 3 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. rxreg_interrupt1_enable 4 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. miscreg_interrupt1_enable 5 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. wheelreg_interrupt1_enable 6 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. clkreg_interrupt1_enable 7 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. tdmreg_interrupt1_enable 8 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. mastreg_interrupt1_enable 9 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. table 57 - interrupt1 enable register
mt90503 data sheet 115 zarlink semiconductor inc. casalarm_interrupt1_enable 10 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. tdmalarm_interrupt1_enable 11 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. clkrecovalarm_interrupt1_enable 12 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. aal0alarm_interrupt1_enable 13 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. erroralarm_interrupt1_enable 14 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[0]. reserved 15 rw reserved. must always be "0" address: 22ch label: interrupt2_enable reset value: 0000h label bit position type description cpureg_interrupt2_enable 0 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. mainreg_interrupt2_enable 1 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. utoreg_interrupt2_enable 2 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. txreg_interrupt2_enable 3 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. rxreg_interrupt2_enable 4 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. miscreg_interrupt2_enable 5 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. wheelreg_interrupt2_enable 6 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. clkreg_interrupt2_enable 7 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. table 58 - interrupt2 enable register address: 228h label: interrupt1_enable reset value: 0000h label bit position type description table 57 - interrupt1 enable register (continued)
mt90503 data sheet 116 zarlink semiconductor inc. tdmreg_interrupt2_enable 8 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. mastreg_interrupt2_enable 9 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. casalarm_interrupt2_enable 10 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. tdmalarm_interrupt2_enable 11 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. clkrecovalarm_interrupt2_ena ble 12 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. aal0alarm_interrupt2_enable 13 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. erroralarm_interrupt2_enable 14 rw when '1' and the corresponding interrupt active is '1', an interrupt will be generated on cpu_int[1]. reserved 15 rw reserved. must always be "0" address: 230h label: utopia_clock1 reset value: 0000h label bit position type description utopia_porta_clk_oe 0 rw 0'=tri-state the txa_clk and rxa_clk; '1'=drive the txa_clk and rxa_clk. this should only be enabled if the chip is to drive these clocks, and only after the clock generation has been correctly programmed. utopia_portb_clk_oe 1 rw 0'=tri-state the txb_clk and rxb_clk; '1'=drive the txb_clk and rxb_clk. this should only be enabled if the chip is to drive these clocks, and only after the clock generation has been correctly programmed. utopia_portc_clk_oe 2 rw this bit must be ?0? as utopia port c clocks must be input only. table 59 - utopia clock register address: 22ch label: interrupt2_enable reset value: 0000h label bit position type description table 58 - interrupt2 enable register (continued)
mt90503 data sheet 117 zarlink semiconductor inc. utopia_txa_clk_select[1:0] 4:3 rw "00" = select clock divisor a; "01" = select clock divisor b; "10" = select clock divisor c; "11" = reserved. there are 3 integer clock divisors used to generate the utopia clocks, and each of the 6 utopia clocks can be selected as any one of the 3. utopia_txb_clk_select[1:0] 6:5 rw "00" = select clock divisor a; "01" = select clock divisor b; "10" = select clock divisor c; "11" = reserved. there are 3 integer clock divisors used to generate the utopia clocks, and each of the 6 utopia clocks can be selected as any one of the 3. utopia_txc_clk_select[1:0] 8:7 rw reserved. utopia_rxa_clk_select[1:0] 10:9 rw "00" = select clock divisor a; "01" = select clock divisor b; "10" = select clock divisor c; "11" = reserved. utopia_rxb_clk_select[1:0] 12:11 rw "00" = select clock divisor a; "01" = select clock divisor b; "10" = select clock divisor c; "11" = reserved. utopia_rxc_clk_select[1:0] 14:13 rw reserved. reserved 15 rw reserved. must always be "0" address: 232h label: utopia_gena reset value: 0001h label bit position type description utopia_clk_diva[5:0] 5:0 rw integer divisor for input ut opia clock. divides the selected clock source. utopia_clk_divisor_load_nowa 6 pul written to '1' when the source, divisor and inv. have been correctly programmed. utopia_clk_inva 7 rw inverts the output of the clock divisor utopia_clk_srca[2:0] 10:8 rw "000"=txa_clk_in; "001"=txb_clk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rx b_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk. utopia_clk_divisor_reseta 11 rw when ?0?, the clock divisor module is held in reset. table 60 - utopia clock generation a register address: 230h label: utopia_clock1 reset value: 0000h label bit position type description table 59 - utopia clock register (continued)
mt90503 data sheet 118 zarlink semiconductor inc. reserved 15:12 rw reserved. must always be "0000" address: 234h label: utopia_genb reset value: 0001h label bit position type description utopia_clk_divb[5:0] 5:0 rw integer divisor for input ut opia clock. divides the selected clock source. utopia_clk_divisor_load_nowb 6 pul written to '1' when the source, divisor and inv. have been correctly programmed. utopia_clk_invb 7 rw inverts the output of the clock divisor utopia_clk_srcb[2:0] 10:8 rw "000"=txa_clk_in; "001"=txb_clk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rxb_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk. utopia_clk_divisor_resetb 11 rw when ?0?, the clock divisor module is held in reset. reserved 15:12 rw reserved. must always be "0000" table 61 - utopia clock generation b register address: 236h label: utopia_genc reset value: 0001h label bit position type description utopia_clk_divc[5:0] 5:0 rw integer divisor for input utopia clock. divides the selected clock source. utopia_clk_divisor_load_nowc 6 pul written to '1' when the source, divisor and inv. have been correctly programmed. utopia_clk_invc 7 rw inverts the output of the clock divisor utopia_clk_srcc[2:0] 10:8 rw "000"=txa_clk_in; "001"=txb_c lk_in; "010"=txc_clk_in; "011"=rxa_clk_in; "100"=rxb_clk_in;"101"=rxc_clk_in; "110"=mclk; "111"=fast_clk. table 62 - utopia clock generation c register address: 232h label: utopia_gena reset value: 0001h label bit position type description table 60 - utopia clock generation a register
mt90503 data sheet 119 zarlink semiconductor inc. utopia_clk_divisor_resetc 11 rw when ?0?, the clock divisor module is held in reset. reserved 15:12 rw reserved. must always be "0000" address: 240h label: cmem_parity0 reset value: 0000h label bit position type description cmem_parity_conf[1:0] 1:0 rw 0' = parity bits; '1' = user data. in normal chip operation, this field should be set to "00", because the chip does not use the parity bits of the control memory. cmem_parity_generation_add_mask [18:16] 4:2 rw mask of address bits [18:16] to be used to generate parity for the control memory. a '1' in one of these bits indicates that the corresponding address bit will be used to generate parity. reserved 7:5 ro reserved. must always be "0000" cmem_parity_generation_data_mask 15:8 rw mask of data bits to be used to generate parity for the control memory. a '1' in one of these bits indicates that the data bi t will be used to generate parity. table 63 - control memory parity0 register address: 242h label: cmem_parity1 reset value: 0000h label bit position type description cmem_parity_generation_add_mask [15:0] 15:0 rw mask of address bits [15:0] to be used to generate parity for the control memory. a '1' in one of these bits indicates that the corresponding address bit will be used to generate parity. table 64 - control memory parity1 register address: 236h label: utopia_genc reset value: 0001h label bit position type description table 62 - utopia clock generation c register
mt90503 data sheet 120 zarlink semiconductor inc. address: 244h label: cmem_conf reset value: 0010h label bit position type description cmem_add_lines 1:0 rw "11" = 1 mb per chip; "10" = 512 kb per chip; "01" = 256kb per chip; "00" = 128 kb per chip cmem_mem_type 3:2 rw "00" = flowthrough zbt; "01" = flowthrough ssram; "10" = pipelined zbt; "11" = pipelined ssram. cmem_rw_ta 4 rw 0 = no read/write turn-around cycle s; 1 = 1 read/write turn-around cycle. reserved 15:5 ro reserved. always read as "0000_0000_000" table 65 - control memory configuration register address: 248h label: dmem_parity0 reset value: 0000h label bit position type description dmem_parity_conf[1:0] 1:0 rw 0' = parity bits; '1' = user data. dmem_parity_generation_add_mask [20:16] 6:2 rw mask of address bits [20:16] to be used to generate parity for the data memory. a '1' in one of these bits indicates that the corresponding address bit will be used to generate parity. reserved 7 ro reserved. always read as "0" dmem_parity_generation_data_mask 15:8 rw mask of data bits to be used to generate parity for the data memory. a '1' in one of these bits indicates that the corresponding data bit will be used to generate parity. table 66 - data memory parity 0 register
mt90503 data sheet 121 zarlink semiconductor inc. 5.5.3 utopia registers address: 24ah label: dmem_parity1 reset value: 0000h label bit position type description dmem_parity_generation_add_mask [15:0] 15:0 rw mask of address bits [15:0] to be used to generate parity for the data memory. a '1' in one of these bits indicates that the corresponding address bit will be used to generate parity. table 67 - data memory parity 1 register address: 24ch label: dmem_conf reset value: 0010h label bit position type description dmem_add_lines 1:0 rw "11" = 1 mb per chip; "10" = 512 kb per chip; "01" = 256kb per chip; "00" = 128 kb per chip dmem_mem_type 3:2 rw "00" = flowthrough zbt; "01" = flowthrough ssram; "10" = pipelined zbt; "11" = pipelined ssram. dmem_rw_ta 4 rw 0 = no read/write turn-around c ycles; 1 = 1 read/write turn-around cycle. reserved 15:5 ro reserved. always read as "0000_0000_000" table 68 - data memory configuration register address: 300h label: control reset value: 0900h label bit position type description rxa_ena 0 rw enables utopia port rxa rxa_sar 1 rw 0' = chip acts as phy, '1' = chip acts as sar rxa_width 2 rw 0' = 8-bit utopia bus, '1' = 16-bit utopia bus rxb_ena 3 rw enables utopia port rxb rxb_sar 4 rw 0' = chip acts as phy, '1' = chip acts as sar rxb_width 5 rw 0' = 8-bit utopia bus, '1' = 16-bit utopia bus table 69 - utopia control register
mt90503 data sheet 122 zarlink semiconductor inc. txa_sar 6 rw 0' = chip acts as phy, '1' = chip acts as sar txa_width 7 rw 0' = 8-bit utopia bus, '1' = 16-bit utopia bus txa_multiphy 8 rw 0' = always drive dat/par/soc pins; '1' = only drive when selected. only applicable when chip is in phy mode. txb_sar 9 rw 0' = chip acts as phy, '1' = chip acts as sar txb_width 10 rw 0' = 8-bit utopia bus, '1' = 16-bit utopia bus txb_multiphy 11 rw 0' = always drive dat/par/soc pins; '1' = only drive when selected. only applicable when chip is in phy mode. add_pin_ena 12 rw if '1', utopia port a is level-2 wi th addressing. when this bit is set, rxb_width and txb_width must be '0'. reserved 13 rw reserved. must always be "0" null_cell_elim 14 rw when '1', all cells with vpi and vci equal to '0' will be discarded. otherwise, they will be kept and treated normally. test_status 15 ts when '1', all the status bits in the register will be set. address: 302h label: control1 reset value: 0008h label bit position type description rxc_ena 0 rw enables utopia port rxc rxc_sar 1 rw 0' = chip acts as phy, '1' = chip acts as sar txc_sar 2 rw 0' = chip acts as phy, '1' = chip acts as sar txc_multiphy 3 rw 0' = always drive dat/par/soc pins; '1' = only drive when selected. only applicable when chip is in phy mode. uto_output_enable 4 rw 0' tri-states the ena or clav pin driven by the chip. '1' drives. this bit should be set to '1' af ter all phy/sar register bits have been programmed, but before all rx_ena bits are set. phy_alarm_pol 6:5 rw "00" = phy alarm disabled, "01" = phy alarm active-high, "10" = phy alarm active-low, "11" = reserved. table 70 - utopia control1 register address: 300h label: control reset value: 0900h label bit position type description table 69 - utopia control register (continued)
mt90503 data sheet 123 zarlink semiconductor inc. long_lut_entries 7 rw when '0', lut entries are 4 bytes long. when '1', lut entries are 8 bytes long. long lut entries should only be used if header translation is to be performed. rxa_nni_null_elim 8 rw 1' consider nni vpi bits for null ce ll elimination for port rxa. if '0', the high 4 bits of the header (g fc field) will be ignored for null cell elimination. rxb_nni_null_elim 9 rw 1' consider nni vpi bits for null ce ll elimination for port rxb. if '0', the high 4 bits of the header (g fc field) will be ignored for null cell elimination. rxc_nni_null_elim 10 rw 1' consider nni vpi bits for null ce ll elimination for port rxc. if '0', the high 4 bits of the header (g fc field) will be ignored for null cell elimination. phya_tx_led_conf 11 rw when '0', phya_tx_led pin functions as a led. when '1', functions as gpio. phya_rx_led_conf 12 rw when '0', phya_rx_led pin functions as a led. when '1', functions as gpio. phyb_tx_led_conf 13 rw when '0', phyb_tx_led pin functions as a led. when '1', functions as gpio. phyb_rx_led_conf 14 rw when '0', phyb_rx_led pin functions as a led. when '1', functions as gpio. reserved 15 rw reserved. must always be "0" address: 304h label: status0 reset value: 0000h label bit position type description rx_cell_loss 0 rol indicates an overflow in the buffer from utopia to the rx sar outa_cell_loss 1 rol indicates an overflow in the output buffer for port txa outb_cell_loss 2 rol indicates an overflow in the output buffer for port txb outc_cell_loss 3 rol indicates an overflow in the output buffer for port txc cell_loss_rollover 4 crl indicates that the cell_loss_ counter register has wrapped table 71 - utopia status 0 register address: 302h label: control1 reset value: 0008h label bit position type description table 70 - utopia control1 register (continued)
mt90503 data sheet 124 zarlink semiconductor inc. tx_arr_rollover 5 crl indicates that the tx_sar_cel l_arrival register has wrapped rx_dep_rollover 6 crl indicates that the rx_sar_cell_ departure register has wrapped ia_arr_rollover 7 crl indicates that the porta_cell _arrival register has wrapped oa_dep_rollover 8 crl indicates that the porta_cell _departure register has wrapped ib_arr_rollover 9 crl indicates that the portb_ce ll_arrival regi ster has wrapped ob_dep_rollover 10 crl indicates that the portb_cell _departure register has wrapped ic_arr_rollover 11 crl indicates that the portc_cell _arrival register has wrapped oc_dep_rollover 12 crl indicates that the portc_cell _departure regist er has wrapped rxa_parity_error 13 rol indicates a parity error on port rxa rxb_parity_error 14 rol indicates a parity error on port rxb rxc_parity_error 15 rol indicates a parity error on port rxc address: 30ch label: status2 reset value: 0000h label bit position type description phy_alarma 0 rolo this bit is set when phya_alm pin is active. active polarity is determined by phy_al arm_pol register phy_alarmb 1 rolo this bit is set when phyb_alm pin is active. active polarity is determined by phy_al arm_pol register test_a_bit 2 rol bit is set when look-up engine gives a pulse on clock recovery vc a. used for tests. test_b_bit 3 rol bit is set when look-up engine gives a pulse on clock recovery vc b. used for tests. reserved 15:4 rw reserved. must always be "0000_0000_0000" table 72 - utopia status 2 register address: 30eh label: status2_ie reset value: 0000h table 73 - utopia interrupt enable 2 register address: 304h label: status0 reset value: 0000h label bit position type description table 71 - utopia status 0 register (continued)
mt90503 data sheet 125 zarlink semiconductor inc. label bit position type description phy_alarma_ie 0 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. phy_alarmb_ie 1 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. test_a_bit_ie 2 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. test_b_bit_ie 3 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. reserved 15:4 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. address: 310h label: counters reset value: 0000h label bit position type description emul_mode 1:0 emo indicates state of counter s and status bits. "00" = normal mode, "01" = reset, "1x" = test mode. these bits are only present for tests and should never be used. cell_loss_emul 2 emu when emul_mode = "11", writing '1' to this bit will increment the cell_loss counter by 1 tx_arr_emul 3 emu when emul_mode = "11", writing '1' to this bit will increment the tx_arr counter by 1 rx_dep_emul 4 emu when emul_mode = "11", writing '1' to this bit will increment the rx_dep counter by 1 ia_arr_emul 5 emu when emul_mode = "11", writing '1' to this bit will increment the ia_arr counter by 1 oa_dep_emul 6 emu when emul_mode = "11", writing '1' to this bit will increment the oa_dep counter by 1 ib_arr_emul 7 emu when emul_mode = "11", writing '1' to this bit will increment the ib_arr counter by 1 ob_dep_emul 8 emu when emul_mode = "11", writing '1' to this bit will increment the ob_dep counter by 1 ic_arr_emul 9 emu when emul_mode = "11", writing '1' to this bit will increment the ic_arr counter by 1 oc_dep_emul 10 emu when emul_mode = "11", writing '1' to this bit will increment the oc_dep counter by 1 reserved 15:11 rw reserved. must always be "0000_0" table 74 - utopia counters register table 73 - utopia interrupt enable 2 register
mt90503 data sheet 126 zarlink semiconductor inc. address: 312h label: cell_loss_counters reset value: 0000h label bit position type description cell_loss 15:0 cnt counts the number of cells lost due to fifo overflows. this includes the output fifos from t he look-up engine to the: rx sar, ports txa, txb, txc. table 75 - cell loss counters register address: 320h label: porta_look_up_base reset value: 0000h label bit position type description luta_base 15:0 rw bits 19:4 of the address of t he look-up table for port a. table 76 - port a look up table address register address: 322h label: porta_num_vpi_vci_bits reset value: 0000h label bit position type description num_vpi_vci_bits 15:0 rw indicates the total number of bi ts that are used to decode the look-up address for port a. 0001h = 1 bit used, ffffh = 16 bits used. when subtracted from vci _n, this indicates the number of vpi bits used. table 77 - port a vpi/vci identification register address: 324h label: porta_concatenation reset value: 0000h label bit position type description vci_na 4:0 rw indicates the number of vci bits used to decode the look-up address for port a. table 78 - port a concatenation register
mt90503 data sheet 127 zarlink semiconductor inc. reserved 15:5 rw reserved. must always be "0000_0000_000" address: 328h label: porta_vpi_match reset value: 0000h label bit position type description vpi_matcha 11:0 rw for a cell from port a to be considered valid, any bits in its vpi whose corresponding bits in reg 32ah are '1' must have the value contained in this register. reserved 15:12 rw reserved. must always be "0000" table 79 - port a vpi match register address: 32ah label: porta_vci_mask reset value: 0000h label bit position type description vpi_maska 11:0 rw for a cell from port a to be considered valid, any bits in its vpi whose corresponding bits in this register are '1' must have the value contained in reg 328h. reserved 15:12 rw reserved. must always be "0000" table 80 - port a vci mask register address: 32ch label: porta_vci_match reset value: 0000h label bit position type description vci_matcha 15:0 rw for a cell from port a to be considered valid, any bits in its vci whose corresponding bits in reg 32eh are '1' must have the value contained in this register. table 81 - port a vci match register address: 324h label: porta_concatenation reset value: 0000h label bit position type description table 78 - port a concatenation register
mt90503 data sheet 128 zarlink semiconductor inc. address: 32eh label: porta_vci_mask reset value: 0000h label bit position type description vci_maska 15:0 rw for a cell from port a to be considered valid, any bits in its vci whose corresponding bits in this register are '1' must have the value contained in reg 32ch. table 82 - port a vci mask register address: 330h label: porta_cell_arrival_high reset value: 0000h label bit position type description ia_arr[31:16] 15:0 cnt freerunning counter of the number of cells received on port a. table 83 - port a cell arrival counter high register address: 332h label: porta_cell_arrival_low reset value: 0000h label bit position type description ia_arr[15:0] 15:0 cnt freerunning counter of the number of cells received on port a. table 84 - port a cell arrival counter low register address: 334h label: porta_cell_departure_high reset value: 0000h label bit position type description oa_dep[31:16] 15:0 cnt freerunning counter of the number of cells transmitted on port a. table 85 - port a cell departure counter high register
mt90503 data sheet 129 zarlink semiconductor inc. address: 336h label: porta_cell_departure_low reset value: 0000h label bit position type description oa_dep[15:0] 15:0 cnt freerunning counter of the numbe r of cells transmitted on port a. table 86 - port a cell departure low register address: 338h label: porta_overflow0 reset value: 0000h label bit position type description ia_rx_cell_max 4:0 rw if the cell fill of the rx sar out put fifo becomes greater than this value, cells from the port a inpu t fifo will be blocked. 0h = no backpressure ia_oa_cell_max 9:5 rw if the cell fill of the port a out put fifo becomes greater than this value, cells from the port a inpu t fifo will be blocked. 0h = no backpressure ia_ob_cell_max 14:10 rw if the cell fill of the port b out put fifo becomes greater than this value, cells from the port a inpu t fifo will be blocked. 0h = no backpressure reserved 15 rw reserved. must always be "0" table 87 - port a overflow0 register address: 33ah label: porta_overflow1 reset value: 0000h label bit position type description ia_oc_cell_max 4:0 rw if the cell fill of the port c output fifo becomes greater than this value, cells from the port a inpu t fifo will be blocked. 0h = no backpressure reserved 15:5 rw reserved. must always be "0000_0000_000" table 88 - port a overflow1 register
mt90503 data sheet 130 zarlink semiconductor inc. address: 33ch label: porta_address reset value: 0000h label bit position type description porta_add 4:0 rw utopia address to which the chip will repond when programmed as a level-2 phy. reserved 15:5 rw reserved. must always be "0000_0000_000" table 89 - port a address register address: 340h label: portb_look_up_b reset value: 0000h label bit position type description lutb_base 15:0 rw bits 19:4 of the address of t he look-up table for port b. table 90 - port b look up table register address: 342h label: portb_num_vpi_vci_bits reset value: 0000h label bit position type description num_vpi_vci_bits 15:0 rw indicates the total number of bi ts that are used to decode the look-up address for port b. 0001 h = 1 bit used, ffffh = 16 bits used. when subtracted from vci _n, this indicates the number of vpi bits used. table 91 - port b vpi/vci identification register address: 344h label: portb_concatenation reset value: 0000h label bit position type description vci_nb 4:0 rw indicates the number of vci bits used to decode the look-up address for port b. reserved 15:5 rw reserved. must always be "0000_0000_000" table 92 - port b concatenation register
mt90503 data sheet 131 zarlink semiconductor inc. address: 348h label: portb_vpi_match reset value: 0000h label bit position type description vpi_matchb 11:0 rw for a cell from port b to be considered valid, any bits in its vpi whose corresponding bits in reg 34ah are '1' must have the value contained in this register. reserved 15:12 rw reserved. must always be "0000" table 93 - port b vpi match register address: 34ah label: portb_vpi_mask reset value: 0000h label bit position type description vpi_maskb 11:0 rw for a cell from port b to be considered valid, any bits in its vpi whose corresponding bits in this register are '1' must have the value contained in reg 348h. reserved 15:12 rw reserved. must always be "0000" table 94 - port b vpi mask register address: 34ch label: portb_vci_match reset value: 0000h label bit position type description vci_matchb 15:0 rw for a cell from port b to be considered valid, any bits in its vci whose corresponding bits in reg 34eh are '1' must have the value contained in this register. table 95 - port b vci match register
mt90503 data sheet 132 zarlink semiconductor inc. address: 34eh label: portb_vci_mask reset value: 0000h label bit position type description vci_maskb 15:0 rw for a cell from port b to be considered valid, any bits in its vci whose corresponding bits in this register are '1' must have the value contained in reg 34ch. table 96 - port b vci mask register address: 350h label: portb_cell_arrival_high reset value: 0000h label bit position type description ib_arr[31:16] 15:0 cnt freerunning counter of the number of cells received on port b. table 97 - port b cell arrival counter high register address: 352h label: portb_cell_arrival_low reset value: 0000h label bit position type description ib_arr[15:0] 15:0 cnt freerunning counter of the number of cells received on port b. table 98 - port b cell arrival counter low register address: 354h label: portb_cell_departure_high reset value: 0000h label bit position type description ob_dep[31:16] 15:0 cnt freerunning counter of the number of cells transmitted on port b. table 99 - port b cell departure counter high register
mt90503 data sheet 133 zarlink semiconductor inc. address: 356h label: portb_cell_departure_low reset value: 0000h label bit position type description ob_dep[15:0] 15:0 cnt freerunning counter of the num ber of cells transmitted on port b. table 100 - port b cell departure counter low register address: 358h label: portb_overflow0 reset value: 0000h label bit position type description ib_rx_cell_max 4:0 rw if the cell fill of the rx sar output fifo becomes greater than this value, cells from the port b input fifo will be blocked. 0h = no backpressure ib_oa_cell_max 9:5 rw if the cell fill of the port a output fifo becomes greater than this value, cells from the port b input fifo will be blocked. 0h = no backpressure ib_ob_cell_max 14:10 rw if the cell fill of the port b output fifo becomes greater than this value, cells from the port b input fifo will be blocked. 0h = no backpressure reserved 15 rw reserved. must always be "0" table 101 - port b overflow0 register address: 35ah label: portb_overflow1 reset value: 0000h label bit position type description ib_oc_cell_max 4:0 rw if the cell fill of the port c output fifo becomes greater than this value, cells from the port b input fifo will be blocked. 0h = no backpressure reserved 15:5 rw reserved. must always be "0000_0000_000" table 102 - port b overflow1 register
mt90503 data sheet 134 zarlink semiconductor inc. address: 360h label: portc_look_up_base reset value: 0000h label bit position type description lutc_base 15:0 rw bits 19:4 of the address of t he look-up table for port c. table 103 - port c look up table register address: 362h label: portc_num_vpi_vci_bits reset value: 0000h label bit position type description num_vpi_vci_bits 15:0 rw indicates the total number of bi ts that are used to decode the look-up address for port c. 0001h = 1 bit used, ffffh = 16 bits used. when subtracted from vci_n, this indicates the number of vpi bits used. table 104 - port c vpi/vci identification register address: 364h label: portc_concatenation reset value: 0000h label bit position type description vci_nc 4:0 rw indicates the number of vci bits used to decode the look-up address for port c. reserved 15:5 rw reserved. must always be "0000_0000_000" table 105 - port c concatenation register address: 368h label: portc_vpi_match reset value: 0000h label bit position type description vpi_matchc 11:0 rw for a cell from port c to be considered valid, any bits in its vpi whose corresponding bits in reg 34ah are '1' must have the value contained in this register. table 106 - port c vpi match register
mt90503 data sheet 135 zarlink semiconductor inc. reserved 15:12 rw reserved. must always be "0000" address: 36ah label: portc_vpi_mask reset value: 0000h label bit position type description vpi_maskc 11:0 rw for a cell from port c to be considered valid, any bits in its vpi whose corresponding bits in this register are '1' must have the value contained in reg 348h. reserved 15:12 rw reserved. must always be "0000" table 107 - port c vpi mask register address: 36ch label: portc_vci_match reset value: 0000h label bit position type description vci_matchc 15:0 rw for a cell from port c to be considered valid, any bits in its vci whose corresponding bits in reg 34eh are '1' must have the value contained in this register. table 108 - port c vci match register address: 36eh label: portc_vci_mask reset value: 0000h label bit position type description vci_maskc 15:0 rw for a cell from port c to be considered valid, any bits in its vci whose corresponding bits in this register are '1' must have the value contained in reg 34ch. table 109 - port c vci match register address: 368h label: portc_vpi_match reset value: 0000h label bit position type description table 106 - port c vpi match register
mt90503 data sheet 136 zarlink semiconductor inc. address: 370h label: portc_cell_arrival_high reset value: 0000h label bit position type description ic_arr[31:16] 15:0 cnt freerunning counter of the numbe r of cells received on port c. table 110 - port c cell arrival counter high register address: 372h label: portc_cell_arrival_low reset value: 0000h label bit position type description ic_arr[15:0] 15:0 cnt freerunning counter of the num ber of cells received on port c. table 111 - port c cell arrival counter low register address: 374h label: portc_cell_departure_high reset value: 0000h label bit position type description oc_dep[31:16] 15:0 cnt freerunning counter of the num ber of cells transmitted on port c. table 112 - port c cell departure counter high register address: 376h label: portc_cell_departure_low reset value: 0000h label bit position type description oc_dep[15:0] 15:0 cnt freerunning counter of the num ber of cells transmitted on port c. table 113 - port c cell departure counter low register
mt90503 data sheet 137 zarlink semiconductor inc. address: 378h label: portc_overflow0 reset value: 0000h label bit position type description ic_rx_cell_max 4:0 rw if the cell fill of the rx sar output fifo becomes greater than this value, cells from the port c input fifo will be blocked. 0h = no backpressure ic_oa_cell_max 9:5 rw if the cell fill of the port a output fifo becomes greater than this value, cells from the port c input fifo will be blocked. 0h = no backpressure ic_ob_cell_max 14:10 rw if the cell fill of the port b output fifo becomes greater than this value, cells from the port c input fifo will be blocked. 0h = no backpressure reserved 15 rw reserved. must always be "0" table 114 - port c overflow0 register address: 37ah label: portc_overflow1 reset value: 0000h label bit position type description ic_oc_cell_max 4:0 rw if the cell fill of the port c output fifo becomes greater than this value, cells from the port c input fifo will be blocked. 0h = no backpressure reserved 15:5 rw reserved. must always be "0000_0000_000" table 115 - port c overflow1 register address: 390h label: tx_sar_cell_arrival_high reset value: 0000h label bit position type description tx_arr[31:16] 15:0 cnt bits [31:16] of tx sar arrival cell counter. counts the number of cells received by ut opia from the tx sar table 116 - tx_sar cell arrival counter high register
mt90503 data sheet 138 zarlink semiconductor inc. address: 392h label: tx_sar_cell_arrival_low reset value: 0000h label bit position type description tx_arr[15:0] 15:0 cnt bits [15:0] of tx sar arri val cell counter. counts the number of cells received by utopia from the tx sar table 117 - tx_sar cell arrival counter low register address: 394h label: rx_sar_cell_departure_high reset value: 0000h label bit position type description rx_dep[31:16] 15:0 cnt bits [31:16] of rx sar departure cell counter. counts the number of cells sent to the rx sar from utopia table 118 - rx_sar cell departure counter high register address: 396h label: rx_sar_cell_departure_low reset value: 0000h label bit position type description rx_dep[15:0] 15:0 cnt bits [15:0] of rx sar departure cell counter. counts the number of cells sent to the rx sar from utopia table 119 - rx_sar cell departure counter low register address: 398h label: tx_sar_overflow reset value: 0000h label bit position type description tx_rx_cell_max 4:0 rw if the cell fill of the rx sar outp ut fifo becomes greater than this value, cells from the tx sar input fifo will be blocked. 0h = no backpressure tx_oa_cell_max 9:5 rw if the cell fill of the po rt a output fifo becomes greater than this value, cells from the tx sar input fifo will be blocked. 0h = no backpressure tx_ob_cell_max 14:10 rw if the cell fill of the po rt b output fifo becomes greater than this value, cells from the tx sar input fifo will be blocked. 0h = no backpressure reserved 15 rw reserved. must always be "0" table 120 - tx_sar overflow0 register
mt90503 data sheet 139 zarlink semiconductor inc. address: 39ah label: tx_sar_overflow reset value: 0000h label bit position type description tx_oc_cell_max 4:0 rw if the cell fill of the port c output fifo becomes greater than this value, cells from the tx sar input fifo will be blocked. 0h = no backpressure reserved 15:5 rw reserved. must always be "0000_0000_000" table 121 - tx_sar overflow1 register address: 3a0h label: hec_byte_control reset value: 0055h label bit position type description hec_mask 7:0 rw value by which the hec generated on utopia will be xored before being transmitted. should match the value used by the phy. reserved 15:8 rw reserved. must always be "0000_0000_0" table 122 - hec byte control register address: 3a2h label: unknown_header_routing reset value: 0000h label bit position type description rxa_ncr 3:0 rw normal cell routing for unknow cells re ceived on port a. "xxx1" = port a, "xx1x" = port b, "x1xx" = port c, "1xxx" rx sar. cells can be broadcast to multiple destinations by setting mult iple bits in this field to '1'. rxb_ncr 7:4 rw normal cell routing for unknow cells re ceived on port b. "xxx1" = port a, "xx1x" = port b, "x1xx" = port c, "1xxx" rx sar. cells can be broadcast to multiple destinations by setting mult iple bits in this field to '1'. rxc_ncr 11:8 rw normal cell routing for unknow cells re ceived on port c. "xxx1" = port a, "xx1x" = port b, "x1xx" = port c, "1xxx" rx sar. cells can be broadcast to multiple destinations by setting mult iple bits in this field to '1'. reserved 15:12 rw reserved. must always be "0000" table 123 - unknown header routing register
mt90503 data sheet 140 zarlink semiconductor inc. address: 3a4h label: unknown_oam_routing reset value: 0000h label bit position type description rxa_ocr 3:0 rw oam cell routing for unknow cells received on port a. "xxx1" = port a, "xx1x" = port b, "x1xx" = port c, "1xxx" rx sar. cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. rxb_ocr 7:4 rw oam cell routing for unknow cells received on port b. "xxx1" = port a, "xx1x" = port b, "x1xx" = port c, "1xxx" rx sar. cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. rxc_ocr 11:8 rw oam cell routing for unknow cells received on port c. "xxx1" = port a, "xx1x" = port b, "x1xx" = port c, "1xxx" rx sar. cells can be broadcast to multiple destinations by setting multiple bits in this field to '1'. reserved 15:12 rw reserved. must always be "0000" table 124 - unknown oam routing register address: 3c0h label: gpio_input0 reset value: 0000h label bit position type description txa_data_input 7:0 ro current level of txa_data pins [15:8] rxa_data_input 15:8 ro current level of rxa_data pins [15:8] table 125 - gpio input0 register address: 3c2h label: gpio_input1 reset value: 0000h label bit position type description txb_data_input 7:0 ro current level of txb_data pins [15:8] rxb_data_input 15:8 ro current level of rxb_data pins [15:8] table 126 - gpio input1 register
mt90503 data sheet 141 zarlink semiconductor inc. address: 3c4h label: gpio_input2 reset value: 0000h label bit position type description phya_alm_input 0 ro current level of phya_alm pin phyb_alm_input 1 ro current level of phya_alm pin phya_tx_led_input 2 ro current level of phya_tx_led pin phya_rx_led_input 3 ro current level of phya_rx_led pin phyb_tx_led_input 4 ro current level of phyb_tx_led pin phyb_rx_led_input 5 ro current level of phyb_rx_led pin reserved 15:6 ro reserved. always read as "0000_0000_00" table 127 - gpio input2 register address: 3c8h label: txa_data_status reset value: 0000h label bit position type description txa_data8_rise 0 rol this bit is set when corresponding pin changes from '0' to '1' txa_data8_fall 1 rol this bit is set when corresponding pin changes from '1' to '0' txa_data9_rise 2 rol this bit is set when corresponding pin changes from '0' to '1' txa_data9_fall 3 rol this bit is set when corresponding pin changes from '1' to '0' txa_data10_rise 4 rol this bit is set when corresponding pin changes from '0' to '1' txa_data10_fall 5 rol this bit is set when corresponding pin changes from '1' to '0' txa_data11_rise 6 rol this bit is set when corresponding pin changes from '0' to '1' txa_data11_fall 7 rol this bit is set when corresponding pin changes from '1' to '0' txa_data12_rise 8 rol this bit is set when corresponding pin changes from '0' to '1' txa_data12_fall 9 rol this bit is set when corresponding pin changes from '1' to '0' txa_data13_rise 10 rol this bit is set when corresponding pin changes from '0' to '1' txa_data13_fall 11 rol this bit is set when corresponding pin changes from '1' to '0' txa_data14_rise 12 rol this bit is set when corresponding pin changes from '0' to '1' txa_data14_fall 13 rol this bit is set when corresponding pin changes from '1' to '0' txa_data15_rise 14 rol this bit is set when corresponding pin changes from '0' to '1' txa_data15_fall 15 rol this bit is set when corresponding pin changes from '1' to '0' table 128 - txa data status register
mt90503 data sheet 142 zarlink semiconductor inc. address: 3cah label: txa_data_status_ie reset value: 0000h label bit position type description txa_data8_rise_ie 0 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data8_fall_ie 1 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data9_rise_ie 2 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data9_fall_ie 3 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data10_rise_ie 4 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data10_fall_ie 5 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data11_rise_ie 6 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data11_fall_ie 7 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txa_data12_rise_ie 8 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data12_fall_ie 9 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data13_rise_ie 10 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data13_fall_ie 11 ie when '1' and the correspon ding status bit is '1', an interrupt will be generated. txa_data14_rise_ie 12 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data14_fall_ie 13 ie when '1' and the correspon ding status bit is '1', an interrupt will be generated. txa_data15_rise_ie 14 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txa_data15_fall_ie 15 ie when '1' and the correspon ding status bit is '1', an interrupt will be generated. table 129 - txa data interrupt enable register
mt90503 data sheet 143 zarlink semiconductor inc. address: 3cch label: rxa_data_status reset value: 0000h label bit position type description rxa_data8_rise 0 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data8_fall 1 rol this bit is set when corresponding pin changes from '1' to '0' rxa_data9_rise 2 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data9_fall 3 rol this bit is set when corresponding pin changes from '1' to '0' rxa_data10_rise 4 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data10_fall 5 rol this bit is set when corresponding pin changes from '1' to '0' rxa_data11_rise 6 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data11_fall 7 rol this bit is set when corresponding pin changes from '1' to '0' rxa_data12_rise 8 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data12_fall 9 rol this bit is set when corresponding pin changes from '1' to '0' rxa_data13_rise 10 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data13_fall 11 rol this bit is set when corresponding pin changes from '1' to '0' rxa_data14_rise 12 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data14_fall 13 rol this bit is set when corresponding pin changes from '1' to '0' rxa_data15_rise 14 rol this bit is set when corresponding pin changes from '0' to '1' rxa_data15_fall 15 rol this bit is set when corresponding pin changes from '1' to '0' table 130 - rxa data status register address: 3ceh label: rxa_data_status_ie reset value: 0000h label bit position type description rxa_data8_rise_ie 0 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data8_fall_ie 1 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxa_data9_rise_ie 2 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. table 131 - rxa data interrupt enable register
mt90503 data sheet 144 zarlink semiconductor inc. rxa_data9_fall_ie 3 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxa_data10_rise_ie 4 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data10_fall_ie 5 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data11_rise_ie 6 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data11_fall_ie 7 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data12_rise_ie 8 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data12_fall_ie 9 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data13_rise_ie 10 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data13_fall_ie 11 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data14_rise_ie 12 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data14_fall_ie 13 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data15_rise_ie 14 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. rxa_data15_fall_ie 15 ie when '1' and the co rresponding status bit is '1', an interrupt will be generated. address: 3d0h label: txb_data_status reset value: 0000h label bit position type description txb_data8_rise 0 rol this bit is set when corresponding pin changes from '0' to '1' txb_data8_fall 1 rol this bit is set when corresponding pin changes from '1' to '0' txb_data9_rise 2 rol this bit is set when corresponding pin changes from '0' to '1' table 132 - txb data status register address: 3ceh label: rxa_data_status_ie reset value: 0000h label bit position type description table 131 - rxa data interrupt enable register (continued)
mt90503 data sheet 145 zarlink semiconductor inc. txb_data9_fall 3 rol this bit is set when corresponding pin changes from '1' to '0' txb_data10_rise 4 rol this bit is set when corresponding pin changes from '0' to '1' txb_data10_fall 5 rol this bit is set when corresponding pin changes from '1' to '0' txb_data11_rise 6 rol this bit is set when corresponding pin changes from '0' to '1' txb_data11_fall 7 rol this bit is set when corresponding pin changes from '1' to '0' txb_data12_rise 8 rol this bit is set when corresponding pin changes from '0' to '1' txb_data12_fall 9 rol this bit is set when corresponding pin changes from '1' to '0' txb_data13_rise 10 rol this bit is set when corresponding pin changes from '0' to '1' txb_data13_fall 11 rol this bit is set when corresponding pin changes from '1' to '0' txb_data14_rise 12 rol this bit is set when corresponding pin changes from '0' to '1' txb_data14_fall 13 rol this bit is set when corresponding pin changes from '1' to '0' txb_data15_rise 14 rol this bit is set when corresponding pin changes from '0' to '1' txb_data15_fall 15 rol this bit is set when corresponding pin changes from '1' to '0' address: 3d2h label: txb_data_status_ie reset value: 0000h label bit position type description txb_data8_rise_ie 0 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data8_fall_ie 1 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data9_rise_ie 2 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data9_fall_ie 3 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data10_rise_ie 4 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. table 133 - txb data interrupt enable register address: 3d0h label: txb_data_status reset value: 0000h label bit position type description table 132 - txb data status register (continued)
mt90503 data sheet 146 zarlink semiconductor inc. txb_data10_fall_ie 5 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data11_rise_ie 6 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data11_fall_ie 7 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data12_rise_ie 8 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data12_fall_ie 9 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data13_rise_ie 10 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data13_fall_ie 11 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data14_rise_ie 12 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data14_fall_ie 13 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data15_rise_ie 14 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. txb_data15_fall_ie 15 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. address: 3d2h label: txb_data_status_ie reset value: 0000h label bit position type description table 133 - txb data interrupt enable register (continued)
mt90503 data sheet 147 zarlink semiconductor inc. address: 3d4h label: rxb_data_status reset value: 0000h label bit position type description rxb_data8_rise 0 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data8_fall 1 rol this bit is set when corresponding pin changes from '1' to '0' rxb_data9_rise 2 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data9_fall 3 rol this bit is set when corresponding pin changes from '1' to '0' rxb_data10_rise 4 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data10_fall 5 rol this bit is set when corresponding pin changes from '1' to '0' rxb_data11_rise 6 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data11_fall 7 rol this bit is set when corresponding pin changes from '1' to '0' rxb_data12_rise 8 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data12_fall 9 rol this bit is set when corresponding pin changes from '1' to '0' rxb_data13_rise 10 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data13_fall 11 rol this bit is set when corresponding pin changes from '1' to '0' rxb_data14_rise 12 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data14_fall 13 rol this bit is set when corresponding pin changes from '1' to '0' rxb_data15_rise 14 rol this bit is set when corresponding pin changes from '0' to '1' rxb_data15_fall 15 rol this bit is set when corresponding pin changes from '1' to '0' table 134 - rxb data status register address: 3d6h label: rxb_data_status_ie reset value: 0000h label bit position type description rxb_data8_rise_ie 0 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data8_fall_ie 1 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data9_rise_ie 2 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data9_fall_ie 3 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. table 135 - rxb data interrupt enable register
mt90503 data sheet 148 zarlink semiconductor inc. rxb_data10_rise_ie 4 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data10_fall_ie 5 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data11_rise_ie 6 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data11_fall_ie 7 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data12_rise_i 8 ie when '1' and the corresponding st atus bit is '1', an interrupt will be generated. rxb_data12_fall_ie 9 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data13_rise_ie 10 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data13_fall_ie 11 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data14_rise_ie 12 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data14_fall_ie 13 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data15_rise_ie 14 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. rxb_data15_fall_ie 15 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. address: 3d8h label: gpio_status reset value: 0000h label bit position type description phya_alm_rise 0 rol this bit is set when corresponding pin changes from '0' to '1' phya_alm_fall 1 rol this bit is set when corresponding pin changes from '1' to '0' phyb_alm_rise 2 rol this bit is set when corresponding pin changes from '0' to '1' phyb_alm_fall 3 rol this bit is set when corresponding pin changes from '1' to '0' phya_tx_led_rise 4 rol this bit is set when corresponding pin changes from '0' to '1' phya_tx_led_fall 5 rol this bit is set when corresponding pin changes from '1' to '0' phya_rx_led_rise 6 rol this bit is set when corresponding pin changes from '0' to '1' phya_rx_led_fall 7 rol this bit is set when corresponding pin changes from '1' to '0' phyb_tx_led_rise 8 rol this bit is set when corresponding pin changes from '0' to '1' table 136 - gpio status register table 135 - rxb data interrupt enable register (continued)
mt90503 data sheet 149 zarlink semiconductor inc. phyb_tx_led_fall 9 rol this bit is set when corresponding pin changes from '1' to '0' phyb_rx_led_rise 10 rol this bit is set when corresponding pin changes from '0' to '1' phyb_rx_led_fall 11 rol this bit is set when corresponding pin changes from '1' to '0' reserved 15:12 rol reserved. always read as "0000" address: 3dah label: gpio_status_ie reset value: 0000h label bit position type description phya_alm_rise_ie 0 ie when '1' and the corresp onding status bit is '1', an interrupt will be generated. phya_alm_fall_ie 1 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phyb_alm_rise_ie 2 ie when '1' and the corresp onding status bit is '1', an interrupt will be generated. phyb_alm_fall_ie 3 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phya_tx_led_rise_ie 4 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phya_tx_led_fall_ie 5 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phya_rx_led_rise_ie 6 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phya_rx_led_fall_ie 7 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phyb_tx_led_rise_ie 8 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phyb_tx_led_fall_ie 9 ie when '1' and the corres ponding status bit is '1', an interrupt will be generated. phyb_rx_led_rise_ie 10 ie when '1' and the corr esponding status bit is '1', an interrupt will be generated. phyb_rx_led_fall_ie 11 ie when '1' and the corr esponding status bit is '1', an interrupt will be generated. table 137 - gpio status register address: 3d8h label: gpio_status reset value: 0000h label bit position type description table 136 - gpio status register (continued)
mt90503 data sheet 150 zarlink semiconductor inc. reserved 15:12 ro reserved. always read as "0000" address: 3e0h label: gpio_output0 reset value: 0000h label bit position type description txa_data_output 7:0 rw this is the value sent out on the pins txa_data [15:8], used in conjuction with the oe bit reserved 15:8 rw reserved. must always be "0000_0000" table 138 - gpio output0 register address: 3e2h label: gpio_output1 reset value: 0000h label bit position type description txb_data_output 7:0 rw this is the value sent out on th e pins txb_data [15:8], used in conjuction with the oe bit reserved 15:8 rw reserved. must always be "0000_0000" table 139 - gpio output1 register address: 3e4h label: gpio_output2 reset value: 0000h label bit position type description phya_tx_led_output 0 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit phya_rx_led_output 1 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit table 140 - gpio output2 register address: 3dah label: gpio_status_ie reset value: 0000h label bit position type description table 137 - gpio status register (continued)
mt90503 data sheet 151 zarlink semiconductor inc. phyb_tx_led_output 2 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit phyb_rx_led_output 3 rw this is the value sent out on the corresponding pin, used in conjuction with the oe bit reserved 15:4 rw reserved. must always be "0000_0000_0000" address: 3e8h label: gpio_oe0 reset value: 0000h label bit position type description txa_data_oe 7:0 rw this is oe bit used to drive the txa_data [15:8] pins reserved 15:8 rw reserved. must always be "0000_0000" table 141 - gpio output enable0 register address: 3eah label: gpio_oe1 reset value: 0000h label bit position type description txb_data_oe 7:0 rw this is oe bit used to dr ive the txb_data [15:8] pins reserved 15:8 rw reserved. must always be "0000_0000" table 142 - gpio output enable1 register address: 3e4h label: gpio_output2 reset value: 0000h label bit position type description table 140 - gpio output2 register (continued)
mt90503 data sheet 152 zarlink semiconductor inc. 5.5.4 tdm registers address: 3ech label: gpio_oe2 reset value: 0000h label bit position type description phya_tx_led_oe 0 rw this is oe bit used to drive the corresponding pin phya_rx_led_oe 1 rw this is oe bit used to drive the corresponding pin phyb_tx_led_oe 2 rw this is oe bit used to drive the corresponding pin phyb_rx_led_oe 3 rw this is oe bit used to drive the corresponding pin reserved 15:4 rw reserved. must always be "0000_0000_0000" table 143 - gpio output enable2 register address: 400h label: control reset value: 0000h label bit position type description global_oe 0 rw ?0' = ct_d[31:0] forced tri-stat e; '1' = ct_d[31:0] may be driven. h100_data_loopback 1 rw ?0' = no ct_d[31:0] loopback; '1 ' = ct_d[31:0] loopback. for test only. tdmie_enable 2 rw ?0' disables tdm process. should only be set to '1' when cam has been programmed stream_mode 4:3 rw "00" = 32 streams, "01" = 16 streams, "10" = 4 streams, "11" = reserved. this register is only used for tests: in real operation, it should be left to "00" (32 streams). reserved 14:5 rw reserved. must always be "0000_0000_00" test_status 15 ts when '1', all the status bits in the register will be set. table 144 - tdm control register
mt90503 data sheet 153 zarlink semiconductor inc. address: 402h label: status0 reset value: 0000h label bit position type description tdm_out_of_bandwidth0 0 rol indicates that the tdm state mach ine is out of bandwidth. fatal chip error, usually due to mclk frequency being too low. cut_vc_detected 1 rol this bit is set when 255 underruns are detected on a vc whose cam entry has an enabled "cut vc status enable" bit underrun_detected 2 rol underrun reported on a voice channel on the atm link. cas_underrun_detected 3 rol underrun reported on cas bits on the atm link. rdatamem_overflow 4 rol overflow in the tdm rx internal data memory. fatal chip error. tdmtxpip_overflow 5 rol overflow in the tdm tx data memory access cache. fatal chip error. tdmrxpip_overflow 6 rol overflow in the tdm rx data memory access cache. fatal chip error. reserved 15:7 rol reserved. always read as "0000_0000_0" table 145 - tdm status register address: 408h label: cut_vc_tsst reset value: 0000h label bit position type description tsst_number_cut_vc 11:0 ro indicates the tsst on which the last cut vc error occurred. reserved 15:12 ro reserved. always read as "0000" table 146 - cut vc tsst register address: 40ah label: underrun_tsst reset value: 0000h label bit position type description tsst_number_underrun 11:0 ro indicates the tsst on which the last underrun error occurred. reserved 15:12 ro reserved. always read as "0000" table 147 - tsst underrun register
mt90503 data sheet 154 zarlink semiconductor inc. address: 40ch label: cas_underrun_tsst reset value: 0000h label bit position type description tsst_number_cas_underrun 11:0 ro indicates the tsst on which the last cas underrun error occurred. reserved 15:12 ro reserved. always read as "0000" table 148 - tsst cas underrun register address: 410h label: tdmint_reg0 reset value: 0000h label bit position type description h100_samp_clk_delay_flops 3:0 rw number of flops used = 8 + value of this register. "1111" is reserved for selecting falling edge ct_c8 clock. h100_samp_clk_delay_buff 7:4 rw "1111" is reserved for selecting rising edge ct_c8 clock h100_oe_clk_delay_flops 11:8 rw number of flops used = 8 + value of this register h100_oe_clk_delay_buff 15:12 rw number of delay buffers used in the delay chain. table 149 - tdm interrupt 0 register address: 412h label: tdmint_reg1 reset value: 0000h label bit position type description h100_ts_counter_timeout 6:0 rw number of mclk cycles in 8 ct_c8 clock cycles - 10% h100_oe_override_disable 7 rw '1' = do not tri-state the ct_d pin after every timeslot. to respect the h.100 standard, this should be left to '0'. dstream_0_3_freq 9:8 rw ct_d[3:0] stream clock speed. "00" = 2.048 mhz; "01" = 4.096 mhz; "10" = 8.192 mhz; "11" = reserved. dstream_4_7_freq 11:10 rw ct_d[7:4] stream clock speed. "00" = 2.048 mhz; "01" = 4.096 mhz; "10" = 8.192 mhz; "11" = reserved. dstream_8_11_freq 13:12 rw ct_d[11:8] stream clock speed. "00" = 2.048 mhz; "01" = 4.096 mhz; "10" = 8.192 mhz; "11" = reserved. table 150 - tdm interrupt 1 register
mt90503 data sheet 155 zarlink semiconductor inc. dstream_12_15_freq 15:14 rw ct_d[15:12] stream clock speed. "00" = 2.048 mhz; "01" = 4.096 mhz; "10" = 8.192 mhz; "11" = reserved. address: 420h label: tdmie_misc reset value: 00ffh label bit position type description null_byte 7:0 rw null byte with which the chip will pad if underruns occur and null byte padding is chosen. cas_enable_position 10:8 rw position of the cas enable bit wi thin the byte on the tdm bus. the cas nibble will be contained in the nibble in which the enable is not present. for example, if the enable is contained in bit 6, then the nibble will be in bits 3:0. cas_enable_polarity 11 rw polarity of the cas enable bit on the tdm bus. reserved 15:12 rw reserved. must always be "0000" table 151 - tdm interrupt enable misc. register address: 460h label: pnt_ro reset value: 0000h label bit positio n type description txsar_write_pnt_pcm_monitor [9:0] 9:0 ro the current value of the tdm write pointer sent to the tx sar. only used for tests. reserved 15:10 ro reserved. always read as "0000_00" table 152 - tdm write pointer 0 register address: 412h label: tdmint_reg1 reset value: 0000h label bit position type description table 150 - tdm interrupt 1 register (continued)
mt90503 data sheet 156 zarlink semiconductor inc. 5.5.5 tx_sar registers address: 462h label: txsar_pnt_fire reset value: 0000h label bit positio n type description txsar_write_pnt_insert[9:0] 9:0 rw the test value of the tdm wr ite pointer sent to the tx sar. only used for tests. txsar_write_pnt_insert_ena 10 rw when '1', the above pointer w ill be sent to the tx sar instead of the valid pointer. only used for tests. reserved 15:11 ro reserved. always read as "0000_00" table 153 - tdm write pointer 1 register address: 464h label: rxsar_pnt_fire reset value: 0000h label bit position type description rxsar_write_pnt_insert[14:0] 14:0 rw the test value of the tdm read pointer sent to the rx sar. only used for tests. rxsar_write_pnt_insert_ena 15 rw when '1', the above pointer will be sent to the rx sar instead of the valid pointer. only used for tests. table 154 - tdm read pointer register address: 500h label: control reset value: 0000h label bit position type description reserved 14:0 ro reserved. always read as "0000_0000_0000_000" test_status 15 ts when '1', all the status bits in the register will be set. table 155 - tx_sar control register
mt90503 data sheet 157 zarlink semiconductor inc. address: 502h label: status reset value: 0000h label bit position type description global_tx_slip 0 rol raised when a bad configuration of the offset field in the tx control structure causes the tx sar to read data that has not been written yet. txsarpip_overflow 1 rol overflow in the tx sar data memory access cache. fatal chip error. reserved 15:2 ro reserved. always read as "0000_0000_0000_00" table 156 - tx_sar status register address: 504h label: status_ie reset value: 0000h label bit position type description global_tx_slip_ie 0 ie when '1' and the correspondi ng status bit is '1', an interrupt will be generated. txsarpip_overflow_ie 1 ie when '1' and the correspon ding status bit is '1', an interrupt will be generated. reserved 15:2 ie reserved. always read as ""0000_0000_0000_00" table 157 - tx_sar interrupt enable register address: 506h label: control1 reset value: 0000h label bit position type description reset_band_per 0 pul resets the band_per register field. reserved 15:1 ro reserved. always read as "0000_0000_0000_000" table 158 - tx_sar control 1 register
mt90503 data sheet 158 zarlink semiconductor inc. address: 508h label: data_cell_read reset value: 0000h label bit position type description data_read_pnt 13:0 ro chip's read pointer to the aal0 fifo. reserved 15:14 ro reserved. always read as "00" table 159 - tx_sar data read pointer register address: 50ah label: data_cell_write reset value: 0000h label bit position type description data_write_pnt 13:0 rw cpu's write pointer to the aal0 fifo. reserved 15:14 rw reserved. must always be "00" table 160 - tx_sar data write pointer register address: 50ch label: data_cell_add reset value: 0000h label bit position type description data_add 13:0 rw bits 19:6 of the address of the fifo in external memory reserved 15:14 rw reserved. always read as "00" table 161 - tx_sar data address register address: 50eh label: data_cell_size reset value: 0000h label bit position type description data_size 13:0 rw size of data cell fifo in 1 cell increments. all zeros = 16k cells. minimum 4 cells. reserved 15:14 rw reserved. must always be "00" table 162 - tx_sar data cell size register
mt90503 data sheet 159 zarlink semiconductor inc. 5.5.6 scheduler registers address: 510h label: percentage_of_bandwidth reset value: 0000h label bit position type description band_per 15:0 ro monitor of the maximum number of mclk cycles that it has taken the chip to treat an entire tx sar frame. if this number is greater than mclk (in hz) / 8000, some of the frames are overloaded. table 163 - percent of bandwidth register address: 600h label: control reset value: 0000h label bit position type description test_status 15 ts when '1', all the status bits in the register will be set. table 164 - scheduler test status register address: 602h label: status reset value: 0000h label bit position type description out_of_band 0 rol indicates that the wheel treatmen t is more than fr_late frames late. this means that at least some of the frames in the wheels are overloaded. reserved 15:1 rol reserved. always read as "0000_0000_0000_000" table 165 - scheduler status register address: 604h label: status_ie reset value: 0000h label bit position type description out_of_band_ie 0 ie when '1' and the correspondin g status bit is '1', an interrupt will be generated. reserved 15:1 ie reserved. always read as "0000_0000_0000_000" table 166 - scheduler interrupt enable register
mt90503 data sheet 160 zarlink semiconductor inc. address: 608h label: frame_latency reset value: 0001h label bit position type description fr_late 3:0 rw number of frames by which the chip is allowed to be late. 0h = illegal. reserved 15:4 rw reserved. must always be "0000_0000_0000" table 167 - frame latency register address: 610h label: wheel_info _0 reset value: 0001h label bit position type description wheel0_ena 0 rw enable for wheel 0. wheel0_inf 3:1 rw configuration of wheel 0. "000" = nor mal, "100" = t1, "101" = e1, others reserved.l wheel1_ena 4 rw enable for wheel 1. wheel1_inf 7:5 rw configuration of wheel 1. "000" = nor mal, "100" = t1, "101" = e1, others reserved. wheel2_ena 8 rw enable for wheel 2. wheel2_inf 11:9 rw configuration of wheel 2. "000" = nor mal, "100" = t1, "101" = e1, others reserved. wheel3_ena 12 rw enable for wheel 3. wheel3_inf 15:13 rw configuration of wheel 3. "000" = nor mal, "100" = t1, "101" = e1, others reserved. table 168 - scheduler configuration & enable 0 register address: 612h label: wheel_inf_1 reset value: 0000h label bit position type description wheel4_ena 0 rw enable for wheel 4. wheel4_inf 3:1 rw configuration of wheel 4. "000" = normal,"100" = t1, "101" = e1, others reserved. table 169 - scheduler configuration & enable 1 register
mt90503 data sheet 161 zarlink semiconductor inc. wheel5_ena 4 rw enable for wheel 5. wheel5_inf 7:5 rw configuration of wheel 5. "000 " = normal, "100" = t1, "101" = e1, others reserved. wheel6_ena 8 rw enable for wheel 6. wheel6_inf 11:9 rw configuration of wheel 6. "000" = normal,"100" = t1, "101" = e1, others reserved wheel7_ena 12 rw enable for wheel 7. wheel7_inf 15:13 rw configuration of wheel 7. "000 " = normal, "100" = t1, "101" = e1, others reserved. address: 614h label: wheel_inf_2 reset value: 0000h label bit position type description wheel8_ena 0 rw enable for wheel 8. wheel8_inf 3:1 rw configuration of wheel 8. "000" = normal, "100" = t1, "101" = e1, others reserved. wheel9_ena 4 rw enable for wheel 9. wheel9_inf 7:5 rw configuration of wheel 9. "000" = normal, "100" = t1, "101" = e1, others reserved. wheela_ena 8 rw enable for wheel 10. wheela_inf 11:9 rw configuration of wheel 10. "000" = nor mal, "100" = t1, "101" = e1, others reserved. wheelb_ena 12 rw enable for wheel 11. wheelb_inf 15:13 rw configuration of wheel 11. "000" = nor mal, "100" = t1, "101" = e1, others reserved. table 170 - scheduler configuration & enable 2 register address: 612h label: wheel_inf_1 reset value: 0000h label bit position type description table 169 - scheduler configuration & enable 1 register (continued)
mt90503 data sheet 162 zarlink semiconductor inc. 5.5.7 rx_sar registers address: 616h label: wheel_inf_3 reset value: 0000h label bit position type description wheelc_ena 0 rw enable for wheel 12. wheelc_inf 3:1 rw configuration of wheel 12. "000" = normal, "100" = t1, "101" = e1, others reserved. wheeld_ena 4 rw enable for wheel 13. wheeld_inf 7:5 rw configuration of wheel 13. "000" = normal, "100" = t1, "101" = e1, others reserved. wheele_ena 8 rw enable for wheel 14. wheele_inf 11:9 rw configuration of wheel 14. "000" = normal, "100" = t1, "101" = e1, others reserved. reserved 15:12 rw reserved. must always be "0000" table 171 - scheduler configuration & enable 3 register address: 700h label: control reset value: 0000h label bit position type description always_diagnose 0 rw when '1', an error report structure will be generated for every cell that arrives. used for tests. reserved 14:1 rw reserved. must always be "0000_0000_0000_00" test_status 15 ts when '1', all the status bits in the register will be set. table 172 - rx_sar control register address: 702h label: status reset value: 0000h label bit position type description rxsarpip_overflow 0 rol overflow in the rx sar data memory access cache. fatal chip error. data_fifo_overflow 1 rol overflow in the data cell fifo in external memory. table 173 - rx_sar status register
mt90503 data sheet 163 zarlink semiconductor inc. error_fifo_overflow 2 rol overflow in the error report structure fifo in external memory. reserved 15:3 rol reserved. always read as "0000_0000_0000_0" address: 704h label: status_ie reset value: 0000h label bit position type description rxsarpip_overflow_ie 0 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. data_fifo_overflow_ie 1 ie when '1 ' and the corresponding status bit is '1', an interrupt will be generated. error_fifo_overfl ow_ie 2 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. reserved 15:3 ie reserved. always read as "0000_0000_0000_0" table 174 - rx_sar interrupt enable register address: 00708h label: data_cell_read reset value: 0000h label bit position type description data_read_pnt 13:0 rw the cpu's read pointer to the aal0 cell fifo. reserved 15:14 rw reserved. must always be "00" table 175 - rx_sar data read pointer register address: 702h label: status reset value: 0000h label bit position type description table 173 - rx_sar status register (continued)
mt90503 data sheet 164 zarlink semiconductor inc. address: 70ah label: data_cell_write reset value: 0000h label bit position type description data_write_pnt 13:0 ro the chip's write pointer to the aal0 cell fifo. reserved 15:14 ro reserved. always read as "00" table 176 - rx_sar data write pointer register address: 70ch label: data_cell_add reset value: 0000h label bit position type description data_add 13:0 rw bits 19:6 of the address of the fifo in external memory reserved 15:14 rw reserved. must always be "00" table 177 - rx_sar data address register address: 70eh label: data_cell_size reset value: 0000h label bit position type description data_size 13:0 rw size of data cell fifo in 1 cell increments. all zeros = 16k cells. reserved 15:14 rw reserved. must always be "00" table 178 - rx_sar data cell size register address: 710h label: error_struct_read reset value: 0000h label bit position type description error_read_pnt 15:0 rw the cpu's read pointer to t he error report structure fifo. table 179 - error structure read register
mt90503 data sheet 165 zarlink semiconductor inc. address: 712h label: error_struct_write reset value: 0000h label bit position type description error_write_pnt 15:0 ro the chip's write pointer to t he error report structure fifo. table 180 - error structure write register address: 714h label: error_struct_add_high reset value: 0000h label bit position type description error_add[16] 0 rw bits 19:3 of the address of the error fifo in external memory reserved 15:1 rw reserved. must always be "0000_0000_0000_000" table 181 - error structure address high register address: 716h label: error_struct_add_low reset value: 0000h label bit position type description error_add[15:0] 15:0 rw bits 19:3 of the address of the error fifo in external memory table 182 - error structure address low register address: 718h label: error_struct_size reset value: 0000h label bit position type description error_size 15:0 rw size of the error structure fifo (in number of error structures, 8-bytes each). table 183 - error structure size register
mt90503 data sheet 166 zarlink semiconductor inc. address: 720h label: aal0_timeout_high reset value: 0000h label bit position type description aal0_timeout_period[19:16] 3:0 rw time, in us, that an aal0 cell can wait in the fifo before an alarm is generated. reserved 15:4 rw reserved. must always be "0000_0000_0000" table 184 - aal0 timeout high register address: 722h label: aal0_timeout_low reset value: 0000h label bit position type description aal0_timeout_period[15:0 ] 15:0 rw time, in us, that an aal0 cell can wait in the fifo before an alarm is generated. table 185 - aal0 timeout low register address: 724h label: error_timeout_high reset value: 0000h label bit position type description error_timeout_period[19:16] 3:0 rw time, in us, that an error structure can wait in the fifo before an alarm is generated. reserved 15:4 rw reserved. must always be "0000_0000_0000" table 186 - error timeout high register address: 726h label: error_timeout_low reset value: 0000h label bit position type description error_timeout_period[15:0] 15:0 rw time, in us, that an error structure can wait in the fifo before an alarm is generated. table 187 - error timeout low register
mt90503 data sheet 167 zarlink semiconductor inc. 5.5.8 clock registers address: 730h label: treated_pulses reset value: 0000h label bit position type description aal0_treated_pulse 0 pul written to '1' to indicate that aal0 cell fifo has been treated. another alarm will not be generated until the above timeout has elapsed. error_treated_pulse 1 pul written to '1' to indicate that error structure fifo has been treated. another alarm will not be generated until the above timeout has elapsed. reserved 15:2 pul reserved. always read as "0000_0000_0000_00" table 188 - treated pulses register address: 800h label: control reset value: 0000h label bit position type description reserved 14:0 ro reserved. always read as "0000_0000_0000_00" test_status 15 ts when '1', all the status bits in the register will be set. table 189 - clock control register address: 802h label: status reset value: 0000h label bit position type description mclk_count_alarm0 0 rol indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm0 field. mclk_count_alarm1 1 rol indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm1 field. mclk_count_alarm2 2 rol indicates that bits 31:16 of the mclk_count have reached the value contained in the mclk_count_high_alarm2 field. reserved 15:3 rol reserved. always read as "0000_0000_0000_0" table 190 - clock status register
mt90503 data sheet 168 zarlink semiconductor inc. address: 804h label: status_ie reset value: 0000h label bit position type description mclk_count_alarm0_ie 0 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. mclk_count_alarm1_ie 1 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. mclk_count_alarm2_ie 2 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. reserved 15:3 ie reserved. always read as "0000_0000_0000_0" table 191 - status interrupt enable register address: 806h label: mclk_count_high_alm0 reset value: 0000h label bit position type description mclk_count_high_alarm0 15:0 rw this register in conjuction wi th an interrupt enable can be used as a scheduler or as a periodic interrupt controler. table 192 - mclk alarm 0 register address: 808h label: mclk_count_high reset value: 0000h label bit position type description mclk_count[31:16] 15:0 ro freerunning counter of mclk. table 193 - mclk counter high register address: 80ah label: mclk_count_low reset value: 0000h label bit position type description mclk_count[15:0] 15:0 ro freerunning counter of mclk. table 194 - mclk counter low register
mt90503 data sheet 169 zarlink semiconductor inc. address: 80ch label: mclk_count_high_alm1 reset value: 0000h label bit position type description mclk_count_high_alarm1 15:0 rw this register in conjuction with an interrupt enable can be used as a scheduler or as a periodic interrupt controller. table 195 - mclk alarm 1 register address: 80eh label: mclk_count_high_alm2 reset value: 0000h label bit position type description mclk_count_high_alarm2 15:0 rw this register in conjuction wi th an interrupt enable can be used as a scheduler or as a periodic interrupt controller. table 196 - mclk alarm 2 register address: 810h label: tx_srts_reg0 reset value: 0300h label bit position type description tx_srts_enable 0 rw when '1', tx srts values will be generated at the rate indicated by the div_ p and div_q registers. tx_srts_bus_clk_sel 2:1 rw selects which h.100 bus clock will be used to generate srts. "0x"=ct_c8(which ever is used in slave timing) ; "10" = ct_c8_a; "11"=ct_c8_b. reserved 7:3 rw reserved. must always be "0000_0" tx_srts_fnxi_input_select 13:8 rw selects which pins must be used as the fnxi to generate the tx srts value. see table 28, ?sour ce selection,? on page 89 for a full description. reserved 15:14 rw reserved. must always be "00" table 197 - tx_srts 0 register
mt90503 data sheet 170 zarlink semiconductor inc. address: 812h label: tx_srts_reg1 reset value: 0000h label bit position type description tx_srts_overflow 0 rol this bit will be set by hardware if the number of tx srts values sent by the tx srts generation module is greater than the numbe r of tx srts values read by the tx sar. tx_srts_underflow 1 rol this bit will be set by hardware if the number of tx srts values sent by the tx srts generation module is smaller than the number of tx srts values read by the tx sar. reserved 15:2 rol reserved. always read as "0000_0000_0000_00" table 198 - tx_srts 1 register address: 814h label: tx_srts_reg2 reset value: 0000h label bit position type description tx_srts_overflow_ie 0 ie when '1' and the correspo nding status bit is '1', and interrupt will be generated. tx_srts_underflow_ie 1 ie when '1' and the correspo nding status bit is '1', and interrupt will be generated. reserved 15:2 ie reserved. always read as "0000_0000_0000_00" table 199 - tx_srts 2 register address: 818h label: tx_srts_reg4 reset value: 0001h label bit position type description tx_srts_srts8m8c_div_p 15:0 rw the 8.192 mhz clock on the h.100 bus (ct_c8) must be divided by a number k in order to match the interval of 8 srts carrying cells. for example, a 24 channel aal1 structured fully filled channel would require a k of (3 75 / 24) = 15.625. k must then be converted to the values p and q using the following equation: k = p / q. no rouding errors must be made in this conversion. table 200 - tx_srts 4 register
mt90503 data sheet 171 zarlink semiconductor inc. address: 81ah label: tx_srts_reg5 reset value: 0001h label bit position type description tx_srts_srts8m8c_div_q 15:0 rw see table 200, ?tx_srts 4 register,? on page 170 for a descrption of tx_srts_srts8m8c_div_p. table 201 - tx_srts 5 register address: 820h label: adapsrts0_reg0 reset value: 0000h label bit position type description adapsrts0_adaptive_enable 0 rw when '1', the rx adaptive block 0 is activated. received cells on vcs tagged as clock recovery vc 'a' will generate an adaptive point that will be written to external memory. adapsrts0_rx_srts_enable 1 rw when '1', the rx srts block 0 is activated. received srts values on vcs tagged as clock recovery vc 'a' will be written to external memory. also, local srts value will be generated using of the h.100 clocks. adapsrts0_ignore_crc 2 rw when '1', this bit forces the crc in the aal1 header to be ignored. crc errors are reported no matter the state of this bit. adapsrts0_ignore_parity 3 rw when '1', this bit forces the parity bit in the aal1 header to be ignored. pari ty errors are reported no matter the state of this bit. adapsrts0_ignore_seq_num 4 rw when '1', this bit forces the sequence number t in the aal1 header to be ignored. sequence number errors are reported no matt er the state of this bit. adapsrts0_pclk_loss 5 rw this bit can be directly routed out on a recov_x pin in order to convey the state (good / bad) of the clock generated by the adapsrts block 0. adapsrts0_pclk_divisor_load_now 6 pul when this bit is written to '1', the pclk_div and pclk_frc are loaded into the digital pll used to synthesize the pclk. adapsrts0_pclk_divisor_reset 7 rw when '0', the digital pll used to synthesize pclk is put in reset state. when '1', it is not longer in reset. reserved 15:8 rw reserved. must always be "0000_0000" table 202 - adaptive srts0 0 register
mt90503 data sheet 172 zarlink semiconductor inc. address: 822h label: adapsrts0_reg1 reset value: 0000h label bit position type description adapsrts0_aal1_crc_error 0 rol set when an aal1-byte crc error occurs on cells used in the adapsrts0 block. adapsrts0_aal1_bad_parity 1 rol set when an aal1-byte parity error occurs on cells used in the adapsrts0 block. adapsrts0_single_cell_lost 2 rol set when a single cell loss error occurs on cells used in the adapsrts0 block. adapsrts0_multi_cell_lost 3 rol set when a multiple cell loss error occurs on cells used in the adapsrts0 block. adapsrts0_cell_misinserted 4 rol set when a cell misinsertion error occurs on cells used in the adapsrts0 block. adapsrts0_timeout_flag 5 ro set when a the interval between two cells used in the adapsrts0 block is greater than adapsrts0_time_out_period. this bit is automatically cleared by hardware w hen the timeout condition ceases. adapsrts0_timeout_pulse 6 rol set when a the interval between two cells used in the adapsrts0 block is greater than adapsrts0_time_out_period. adapsrts0_rx_srts _remote_overflo w 7 rol set when two consecutive remote srts value were received, and when the second value could not be stored because the interval was too short. adapsrts0_rx_srts_local_overflow 8 rol set when two consecutive local srts value were received, and when the second value could not be stored because the interval was too short. reserved 15:9 rol reserved. always read as "0000_000" table 203 - adaptive srts0 1 register address: 824h label: adapsrts0_reg2 reset value: 0000h label bit position type description adapsrts0_aal1_crc_error_ie 0 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. table 204 - adaptive srts0 2 register
mt90503 data sheet 173 zarlink semiconductor inc. adapsrts0_aal1_bad_parity_ie 1 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. adapsrts0_single_cell_lost_ie 2 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. adapsrts0_multi_cell_lost_ie 3 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. adapsrts0_cell_misinserted_ie 4 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. reserved 5 ro reserved. always read as "0" adapsrts0_timeout_pulse_ie 6 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. adapsrts0_rx_srts_remote_overflow_i e 7 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. adapsrts0_rx_srts_local_overflow_ie 8 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. reserved 15:9 ie reserved. always read as "0000_000" address: 826h label: adapsrts0_reg3 reset value: 0000h label bit position type description adapsrts0_ref_input_select 5:0 rw in adaptive mode, this field indicates which events the adapsrts0 block will consider as a timing reference. rising edges on the recov_x pins can be used. cell arrival events on clock recovery vc a or b can be used. see table 28, ?source selection,? on page 89" for more details. reserved 7:6 ro reserved. always read as "00" adapsrts0_rx_fnxi_input_select 13:8 rw in srts mode, this selects th e fnxi input used in the rx srts block. see table 28, ?source selection,? on page 89" for more details. reserved 15:14 ro reserved. always read as "00" table 205 - adaptive srts0 3 register address: 824h label: adapsrts0_reg2 reset value: 0000h label bit position type description table 204 - adaptive srts0 2 register (continued)
mt90503 data sheet 174 zarlink semiconductor inc. address: 828h label: adapsrts0_reg4 reset value: 0000h label bit position type description adapsrts0_time_out_period 15:0 rw this value defines the time- out period between two cells in both adaptive and srts mode. unit is 1024 mclk cycles. 0000h will disabled checking. table 206 - adaptive srts0 4 register address: 82ah label: adapsrts0_reg5 reset value: 0000h label bit position type description adapsrts0_adap_pnt_elim_x 7:0 rw in adaptive mode, this value defined how many points will be deleted vs how many points will be kept and written to external memory. it is defined as "keep 1 point out of x". reserved 15:8 rw reserved. must always be "0000_0000" table 207 - adaptive srts0 5 register address: 82ch label: adapsrts0_reg6 reset value: 0001h label bit position type description adapsrts0_srts8m8c_div_p 15:0 rw the clock genera ted by the digital pll (pclk at 8khz) must be divided by a number k in order to match the interval of 8 srts carrying cells. for example, a 24 channel aal1 structured fully filled channel would require a k of (375 / 24) = 15.625 . k must then be converted to the values p and q using the following equation: k = p / q. no rouding errors must be made in this conversion. table 208 - adaptive srts0 6 register
mt90503 data sheet 175 zarlink semiconductor inc. address: 82eh label: adapsrts0_reg7 reset value: 0001h label bit position type description adapsrts0_srts8m8c_div_q 15:0 rw see adapsrts0_srts8m8c_div_p description. table 209 - adaptive srts0 7 register address: 830h label: adapsrts0_reg8 reset value: 2710h label bit position type description adapsrts0_pclk_div 15:0 rw in order to generate pclk, mclk mu st be divided by a factor k. this factor is likely to be fractional. the integer part of k is written in the form x / 65536, where x is written in the adapsrts0_pclk_frc register. table 210 - adaptive srts0 8 register address: 832h label: adapsrts0_reg9 reset value: 0000h label bit position type description adapsrts0_pclk_frc 15:0 rw for a description see adapsrts0_pclk_div adapsrts0_pclk_div above. table 211 - adaptive srts0 9 register address: 840h label: adapsrts1_reg0 reset value: 0000h label bit position type description adapsrts1_adaptive_enable 0 rw see adapsrts0 registers 820h to 83eh. adapsrts1_rx_srts_enable 1 rw adapsrts1_ignore_crc 2 rw adapsrts1_ignore_parity 3 rw table 212 - adaptive srts1 0 register
mt90503 data sheet 176 zarlink semiconductor inc. adapsrts1_ignore_seq_num 4 rw adapsrts1_pclk_loss 5 rw adapsrts1_pclk_divisor_load_now 6 pul adapsrts1_pclk_divisor_reset 7 rw reserved 15:8 rw reserved. must always be "0000_0000" address: 842h label: adapsrts1_reg1 reset value: 0000h label bit position type description adapsrts1_aal1_crc_error 0 rol see address: 822h, table 203, ?adaptive srts0 1 register,? on page 172. adapsrts1_aal1_bad_parity 1 rol adapsrts1_single_cell_lost 2 rol adapsrts1_multi_cell_lost 3 rol adapsrts1_cell_misinserted 4 rol adapsrts1_timeout_flag 5 ro adapsrts1_timeout_pulse 6 rol adapsrts1_rx_srts_remote_overflow 7 rol adapsrts1_rx_srts_local_overflow 8 rol reserved 15:9 rol reserved. always read as "0000_000" table 213 - adaptive srts1 1register address: 840h label: adapsrts1_reg0 reset value: 0000h label bit position type description table 212 - adaptive srts1 0 register (continued)
mt90503 data sheet 177 zarlink semiconductor inc. address: 844h label: adapsrts1_reg2 reset value: 0000h label bit position type description adapsrts1_aal1_crc_error_ie 0 ie adapsrts1_aal1_bad_parity_ie 1 ie adapsrts1_single_cell_lost_ie 2 ie adapsrts1_multi_cell_lost_ie 3 ie see "address: 842h" on page 176. adapsrts1_cell_misinserted_ie 4 ie reserved 5 ro adapsrts1_timeout_pulse_ie 6 ie adapsrts1_rx_srts_remote_overflow_ie 7 ie adapsrts1_rx_srts_local_overflow_ie 8 ie reserved 15:9 ie reserved. always read as "0000_000" table 214 - adaptive srts1 2 register address: 846h label: adapsrts1_reg3 reset value: 0000h label bit position type description adapsrts1_ref_input_select 5:0 rw see "address: 826h" on page 173. reserved 7:6 ro adapsrts1_rx_fnxi_input_select 13:8 rw reserved 15:14 ro table 215 - adaptive srts1 3 register address: 848h label: adapsrts1_reg4 reset value: 0000h label bit position type description adapsrts1_time_out_period 15:0 rw see "address: 828h" on page 174. table 216 - adaptive srts1 4 register
mt90503 data sheet 178 zarlink semiconductor inc. address: 84ah label: adapsrts1_reg5 reset value: 0001h label bit position type description adapsrts1_adap_pnt_elim_x 7:0 rw reserved 15:8 rw reserved. must always be "0000_0000" table 217 - adaptive srts1 5 register address: 84ch label: adapsrts1_reg6 reset value: 0000h label bit position type description adapsrts1_srts8m8c_div_p 15:0 rw see "address: 82ch" on page 174. table 218 - adaptive srts1 6 register address: 84eh label: adapsrts1_reg7 reset value: 0000h label bit position type description adapsrts1_srts8m8c_div_q 15:0 rw see "address: 82eh" on page 175. table 219 - adaptive srts1 7 register address: 850h label: adapsrts1_reg8 reset value: 0000h label bit position type description adapsrts1_pclk_div 15:0 rw see "address: 830h" on page 175. table 220 - adaptive srts1 8 register
mt90503 data sheet 179 zarlink semiconductor inc. address: 852h label: adapsrts1_reg9 reset value: 0000h label bit position type description adapsrts1_pclk_frc 15:0 rw see "address: 832h" on page 175. table 221 - adaptive srts1 9 register address: 860h label: pinmux_reg0 reset value: 0202h label bit position type description pinmux_recov_b_sel 5:0 rw this field selects the recov_b output. see "clockrec source select" page for more details. reserved 7:6 ro reserved. always read as "00". pinmux_recov_a_sel 13:8 rw this field selects the recov_a output. see "clockrec source select" page for more details. reserved 15:14 ro reserved. always read as "00". table 222 - pin mux 0 register address: 862h label: pinmux_reg1 reset value: 0202h label bit position type description pinmux_recov_d_sel 5:0 rw this field selects the recov_d output. see table 28 - "source selection" on page 89 for more details. reserved 7:6 ro reserved. always read as "00" pinmux_recov_c_sel 13:8 rw this field selects the recov_c output. see table 28 - "source selection" on page 89 for more details. reserved 15:14 ro reserved. always read as "00" table 223 - pin mux 1 register
mt90503 data sheet 180 zarlink semiconductor inc. address: 864h label: pinmux_reg2 reset value: 0202h label bit position type description pinmux_recov_f_sel 5:0 rw this field selects the recov_f output. see table 28 - "source selection" on page 89 for more details. reserved 7:6 ro reserved. always read as "00" pinmux_recov_e_sel 13:8 rw this field selects the recov_e output. see table 28 - "source selection" on page 89 for more details. reserved 15:14 ro reserved. always read as "00" table 224 - pin mux 2 register address: 866h label: pinmux_reg3 reset value: 0202h label bit position type description pinmux_recov_h_sel 5:0 rw this field selects the recov_h output. see table 28 - "source selection" on page 89 for more details. reserved 7:6 ro reserved. always read as "00" pinmux_recov_g_sel 13:8 rw this field selects the recov_g output. see table 28 - "source selection" on page 89 for more details. reserved 15:14 ro reserved. always read as "00" table 225 - pin mux 3 register address: 868h label: pinmux_reg4 reset value: 0202h label bit position type description pinmux_ct_netref2_sel 5:0 rw this field selects the ct_netref2 output. see table 28 - "source selection" on page 89 for more details. reserved 7:6 ro reserved. always read as "00" pinmux_ct_netref1_sel 13:8 rw this field selects the ct_netref1 output. see table 28 - "source selection" on page 89 for more details. reserved 15:14 ro reserved. always read as "00" table 226 - pin mux 4 register
mt90503 data sheet 181 zarlink semiconductor inc. address: 86ah label: pinmux_reg5 reset value: 0303h label bit position type description pinmux_local_netref_16m_sel 5:0 rw this field selects the local_ 16m reference feed into the h.100 master circuit. see table 28 - "source selection" on page 89 for more details. reserved 7:6 ro reserved. always read as "00" reserved 13:8 ro reserved. always read as "0000_00" reserved 15:14 ro reserved. always read as "00" table 227 - pin mux 5 register address: 880h label: diviclk0_reg0 reset value: 0300h label bit position type description diviclk0_clk_divisor_load_now 0 pul when this bit is written to '1', the integer clock divisor 0's division value will be loaded into the divisor. diviclk0_clk_divisor_reset 1 rw when this bit is '0', the integer clock divisor 0 is put in reset. must be '1' for normal operation. diviclk0_even_duty_cycle_selec t 2 rw when '1', the duty cycle mo difier will be enabled and will generate a 50% duty cycle output. diviclk0_input_invert_select 3 rw when '1', the input of the integer clock divisor will be inverted before being divided. diviclk0_output_invert_select 4 rw when '1', the output of the integer clock divisor will be inverted before being sent out. reserved 12:7 rw reserved. must always be "0000_00" diviclk0_input_source_select 13:8 rw this field selects the input of the integer clock divisor. see table 28 - "source selection" on page 89 for more details. reserved 15:14 rw reserved. must always be "00" table 228 - integer clock divisor0 0 register
mt90503 data sheet 182 zarlink semiconductor inc. address: 882h label: diviclk0_reg1 reset value: 0000h label bit position type description diviclk0_ext_loss_pulse 0 rolo this bit is set when an exter nal signal indicates that the input of the integer clock divisor is invalid (such as a phy alarm). diviclk0_ext_loss_flag 1 ro same as diviclk0_ext_loss_pulse, but when the error condition ceases, this bit will clear itself. diviclk0_freq_too_high_pulse 2 rolo this bit is set when the integer clock divisor input's frequency is off as compared to the expected frequency (received frequency is too high). diviclk0_freq_too_high_flag 3 ro same as diviclk0_freq_too_high_pulse, but when the error condition ceases, this bit will clear itself. diviclk0_freq_too_low_pulse 4 rolo this bit is set when the integer clock divisor input's frequency is off as compared to the expected frequency (received frequency is too low). diviclk0_freq_too_low_flag 5 ro same as diviclk0_freq_too_low_pulse, but when the error condition ceases, this bit will clear itself. reserved 15:6 ro reserved. always read as "0000_0000_00" table 229 - integer clock divisor0 1 register address: 884h label: diviclk0_reg2 reset value: 0000h label bit position type description diviclk0_ext_loss_pulse_ie 0 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. reserved 1 ro reserved. always read as "00" diviclk0_freq_too_high_pulse_ie 2 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. reserved 3 ro reserved. always read as "00" diviclk0_freq_too_low_pulse_ie 4 ie when '1' and the corresponding status bit is '1', and interrupt will be generated. reserved 5 ro reserved. always read as "00" reserved 15:6 ro reserved. always read as "0000_0000_00" table 230 - integer clock divisor0 2 register
mt90503 data sheet 183 zarlink semiconductor inc. address: 886h label: diviclk0_reg3 reset value: 0000h label bit position type description diviclk0_ext_loss_pulse_genloss 0 rw when set, the corresponding status will cause a loss to be signaled for this diviclk. diviclk0_ext_loss_flag_genloss 1 rw when set, the corresponding status will cause a loss to be signaled for this diviclk. diviclk0_freq_too_high_pulse_genloss 2 rw when set, the corresponding status will cause a loss to be signaled for this diviclk. diviclk0_freq_to o_high_flag_genloss 3 rw when set, the corresponding status will cause a loss to be signaled for this diviclk. diviclk0_freq_too_low_pulse_genloss 4 rw when set, the corresponding status will cause a loss to be signaled for this diviclk. diviclk0_freq_to o_low_flag_genloss 5 rw when set, the corresponding status will cause a loss to be signaled for this diviclk. reserved 15:6 rw reserved. must always be "0000_0000_00" table 231 - integer clock divisor0 3 register address: 888h label: diviclk0_reg4 reset value: 0063h label bit position type description diviclk0_ext_loss_source_select 5:0 rw select's which external pin wi ll signal that the input of the integer clock divisor is good or not. see table 28 - "source selection" on page 89 for more details. diviclk0_ext_loss_ source_polarity 6 rw input of the integer clo ck divisor is considered bad when the select ext_loss signal is active (i.e. equal to this bit). 0 = source loss active low; 1 = source loss active high. diviclk0_output_loss_polarity 7 rw when a loss is detected, the output signal indicating this loss is activated (i.e. th e value is this register is sent out). '0' = output loss ac tive low; '1' = output loss active high. reserved 15:8 rw reserved. must always be "0000_0000" table 232 - integer clock divisor0 4 register
mt90503 data sheet 184 zarlink semiconductor inc. address: 88ah label: diviclk0_reg5 reset value: 0000h label bit position type description diviclk0_clk_div 15:0 rw this is the denominator used to divide the input clock. it ranges from 1 to 65535. table 233 - integer clock divisor0 5 register address: 890h label: diviclk0_reg8 reset value: 0000h label bit position type description diviclk0_freqchck_div 15:0 rw this value will be used to divide the input clock before check it against the frequency of mc lk. the higher the division value, the longer to detect a frequency too high or frequency too low, but the check is mo re precise. 0000h disables frequency checking. table 234 - integer clock divisor0 8 register address: 892h label: diviclk0_reg9 reset value: 0000h label bit position type description diviclk0_freqchck_max_mclk_cycles 15:0 rw this regsiter defines the maximum number of mclk cycles between two rising edges of the input clock divided by diviclk0_freqchck_div. if a second rising edge has not been detected in diviclk0_freqchck_max_mclk_cycles, the diviclk0_freq_too_low will be detected. table 235 - integer clock divisor0 9 register
mt90503 data sheet 185 zarlink semiconductor inc. address: 894h label: diviclk0_reg10 reset value: 0000h label bit position type description diviclk0_freqchck_min_mclk_cycles 15:0 rw this regsiter defines th e minimum number of mclk cycles between two rising edges of the input clock divided by diviclk0_freqch ck_div.if a second rising edge has been detected in less then diviclk0_freqchck_min_mclk_cycles, the diviclk0_freq_too_high will be detected. table 236 - integer clock divisor0 10 register address: 8a0h label: diviclk1_reg0 reset value: 0300h label bit position type description diviclk1_clk_divisor_load_now 0 pul see regsiters 880h to 89eh diviclk1_clk_divisor_reset 1 rw diviclk1_even_duty_cycle_select 2 rw diviclk1_input_invert_select 3 rw diviclk1_output_invert_select 4 rw diviclk1_input_source_select 13:8 rw reserved 15:14 rw reserved. must always be "00" table 237 - integer clock divisor1 0 register address: 8a2h label: diviclk1_reg1 reset value: 0000h label bit position type description diviclk1_ext_loss_pulse 0 rolo see register 882h. diviclk1_ext_loss_flag 1 ro diviclk1_freq_too_high_pulse 2 rolo diviclk1_freq_too_high_flag 3 ro table 238 - integer clock divisor1 1 register
mt90503 data sheet 186 zarlink semiconductor inc. diviclk1_freq_too_low_pulse 4 rolo diviclk1_freq_too_low_flag 5 ro reserved 15:6 ro reserved. always read as "0000_0000_00" address: 8a4h label: diviclk1_reg2 reset value: 0000h label bit position type description diviclk1_ext_loss_pulse_ie 0 ie see register 884h. reserved 1 ro diviclk1_freq_ too_high_pulse_ie 2 ie reserved 3 ro diviclk1_freq_too_low_pulse_ie 4 ie reserved 5 ro reserved 15:6 ro reserved. always read as "0000_0000_00" table 239 - integer clock divisor1 2 register address: 8a6h label: diviclk1_reg3 reset value: 0000h label bit position type description diviclk1_ext_loss_pulse_genloss 0 rw see register 886h. diviclk1_ext_loss_flag_genloss 1 rw diviclk1_freq_too_high_pulse_genloss 2 rw diviclk1_freq_too_h igh_flag_genloss 3 rw diviclk1_freq_too_low_pulse_genloss 4 rw table 240 - integer clock divisor1 3 register address: 8a2h label: diviclk1_reg1 reset value: 0000h label bit position type description table 238 - integer clock divisor1 1 register
mt90503 data sheet 187 zarlink semiconductor inc. diviclk1_freq_too_low_flag_genloss 5 rw reserved 15:6 rw reserved. must always be "0000_0000_00" address: 8a8h label: diviclk1_reg4 reset value: 0063h label bit position type description diviclk1_ext_loss_source_select 5:0 rw see register 888h. diviclk1_ext_loss_source_polarity 6 rw diviclk1_output_l oss_polarity 7 rw reserved 15:8 rw reserved. must always be "0000_0000" table 241 - integer clock divisor1 4 register address: 8aah label: diviclk1_reg5 reset value: 0000h label bit position type description diviclk1_clk_div 15:0 rw see register 88ah. table 242 - integer clock divisor1 5 register address: 8b0h label: diviclk1_reg8 reset value: 0000h label bit position type description diviclk1_freqchck_div 15:0 rw see register 890h. table 243 - integer clock divisor1 8 register address: 8a6h label: diviclk1_reg3 reset value: 0000h label bit position type description table 240 - integer clock divisor1 3 register (continued)
mt90503 data sheet 188 zarlink semiconductor inc. address: 8b2h label: diviclk1_reg9 reset value: 0000h label bit position type description diviclk1_freqchck_max_mclk_cycles 15:0 rw see register 892h. table 244 - integer clock divisor1 9 register address: 8b4h label: diviclk1_reg10 reset value: 0000h label bit position type description diviclk1_freqchck_min_mclk_cycles 15:0 rw see register 894h. table 245 - integer clock divisor1 10 register address: 8c0h label: diviclk2_reg0 reset value: 0300h label bit position type description diviclk2_clk_divisor_load_now 0 pul see registers 880h to 89eh diviclk2_clk_divisor_reset 1 rw diviclk2_even_duty_cycle_select 2 rw diviclk2_input_invert_select 3 rw diviclk2_output_invert_select 4 rw diviclk2_input_source_select 13:8 rw reserved 15:14 rw reserved. must always be "00" table 246 - integer clock divisor2 0 register
mt90503 data sheet 189 zarlink semiconductor inc. address: 8c2h label: diviclk2_reg1 reset value: 0000h label bit position type description diviclk2_ext_loss_pulse 0 rolo see register 8a2h. diviclk2_ext_loss_flag 1 ro diviclk2_freq_too_high_pulse 2 rolo diviclk2_freq_too_high_flag 3 ro diviclk2_freq_too_low_pulse 4 rolo diviclk2_freq_too_low_flag 5 ro reserved 15:6 ro reserved. always read as "0000_0000_00" table 247 - integer clock divisor2 1 register address: 8c4h label: diviclk2_reg2 reset value: 0000h label bit position type description diviclk2_ext_loss_pulse_ie 0 ie see register 8a4h. reserved 1 ro diviclk2_freq_too_high_pulse_ie 2 ie reserved 3 ro diviclk2_freq_too_low_pulse_ie 4 ie reserved 5 ro reserved 15:6 ro reserved. always read as "0000_0000_00" table 248 - integer clock divisor2 2 register
mt90503 data sheet 190 zarlink semiconductor inc. address: 8c6h label: diviclk2_reg3 reset value: 0000h label bit position type description diviclk2_ext_loss_pulse_genloss 0 rw see register 8a6h. diviclk2_ext_loss_flag_genloss 1 rw diviclk2_freq_too_high_pulse_genloss 2 rw diviclk2_freq_to o_high_flag_genloss 3 rw diviclk2_freq_too_low_pulse_genloss 4 rw diviclk2_freq_to o_low_flag_genloss 5 rw reserved 15:6 rw reserved. must always be "0000_0000_00" table 249 - integer clock divisor2 3 register address: 8c8h label: diviclk2_reg4 reset value: 0063h label bit position type description diviclk2_ext_loss_source_select 5:0 rw see register 8a8h. diviclk2_ext_loss_ source_polarity 6 rw diviclk2_output_loss_polarity 7 rw reserved 15:8 rw reserved. must always be "0000_0000" table 250 - integer clock divisor2 4 register address: 8cah label: diviclk2_reg5 reset value: 0001h label bit position type description diviclk2_clk_div 15:0 rw see register 8aah. table 251 - integer clock divisor2 5 register
mt90503 data sheet 191 zarlink semiconductor inc. address: 8d0h label: diviclk2_reg8 reset value: 0000h label bit position type description diviclk2_freqchck_div 15:0 rw see register 8b0h. table 252 - integer clock divisor2 8 register address: 8d2h label: diviclk2_reg9 reset value: 0000h label bit position type description diviclk2_freqchck_max_mclk_cycles 15:0 rw see register 8b2h. table 253 - integer clock divisor2 9 register address: 8d4h label: diviclk2_reg10 reset value: 0000h label bit position type description diviclk2_freqchck_min_mclk_cycles 15:0 rw see register 8b4h. table 254 - integer clock divisor2 10 register address: 8e0h label: tx_srts_debug reset value: 0000h label bit position type description tx_srts_eight_cell_pulse_rol 0 rol only used for tests. tx_srts_fnxi_cnt 11:8 ro only used for tests. reserved 15:12 ro reserved. always read as "0000" table 255 - tx srts debug register
mt90503 data sheet 192 zarlink semiconductor inc. address: 8e4h label: adapsrts0_rx_srts_debug reset value: 0000h label bit position type description adapsrts0_eight_cell_pulse_rol 0 rol only used for tests. adapsrts0_rx_srts_fnxi_cnt 11:8 ro only used for tests. reserved 15:12 ro reserved. always read as "0000" table 256 - rx srts debug 0 register address: 8e8h label: adapsrts1_rx_srts_debug reset value: 0000h label bit position type description adapsrts1_eight_cell_pulse_rol 0 rol only used for tests. adapsrts1_rx_srts_fnxi_cnt 11:8 ro only used for tests. reserved 15:12 ro reserved. always read as "0000" table 257 - rx srts debug 1 register address: 8ech label: adapsrts_aal1_err_debug reset value: 0000h label bit position type description adapsrts0_valid_cell 0 rol only used for tests. adapsrts0_cell_lost 1 rol only used for tests. adapsrts1_valid_cell 2 rol only used for tests. adapsrts1_cell_lost 3 rol only used for tests. reserved 15:4 rol reserved. always read as "0000_0000_0000" table 258 - aal1 error debug register
mt90503 data sheet 193 zarlink semiconductor inc. 5.5.9 miscellaneous registers address: 900h label: control reset value: 0000h label bit position type description test_status 15 ts when '1', all the status bits in the register will be set. table 259 - miscellaneous control register address: 902h label: err_reg0 reset value: 0000h label bit position type description adap_srts_remote0_mem_overflow 0 rol indicates that the chip did not have time to write an adaptive point structure before the next one was generated. adap_srts_remote1_mem_overflow 1 rol indicates that the chip did not have time to write an adaptive point structure before the next one was generated. srts_local0_mem_overflow 2 rol indicates that the srts value buffer overflowed. srts_local1_mem_overflow 3 rol indicates that the srts value buffer overflowed. cas_mem_overflow 4 rol indicates that the cas change memory overflowed. silent_tone_error 5 rol new silent tones were requested before the current ones could be fetched. reserved 15:6 rol reserved. always read as "0000_0000_00" table 260 - m iscellaneous error register address: 908h label: silent_tone_reg2 reset value: 0000h label bit position type description silent_size 15:0 rw size of the silent tone buffers , in bytes minus 1. 0 means 1 byte; ffffh means 10000h bytes. table 261 - silent tone 2 register
mt90503 data sheet 194 zarlink semiconductor inc. address: 90ah label: silent_tone_reg3 reset value: 0000h label bit position type description silent_base_add_15_0 15:0 rw the base address of the silent tone buffers (in words). table 262 - silent tone 3 register address: 90ch label: silent_tone_reg3 reset value: 0000h label bit position type description silent_base_add_18_16 2:0 rw the base address of the silent tone buffers (in words). reserved 15:3 rw reserved. must always be "0000_0000_0000_0" table 263 - silent tone 4 register address: 90eh label: as0_srts_reg0 reset value: 0000h label bit position type description adap_srts0_size 15:0 rw size of the adaptive point/srts value buffer minus one. 0 means 1; ffffh means 10000h. table 264 - adaptive point/srts value 0 register address: 910h label: as0_srts_reg1 reset value: 0000h label bit position type description adap_srts0_base_add_15_0 15:0 rw the base address of the adaptive point/srts value buffer (in points or srts values). note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. table 265 - adaptive point/srts base address low 0 register
mt90503 data sheet 195 zarlink semiconductor inc. address: 912h label: as0_srts_reg2 reset value: 0000h label bit position type description adap_srts0_base_add_18_16 2:0 rw the base address of the adaptive point/srts value buffer (in points or srts values). note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. reserved 15:3 rw reserved. must always be "0000_0000_0000_0" table 266 - adaptive point/srts base address high 0 register address: 914h label: as0_srts_reg3 reset value: 0000h label bit position type description adap_srts_remote0_write_pnt 15:0 ro the chip's write pointer to the adaptive point/srts value buffer. table 267 - adaptive point/srts write pointer 0 register address: 916h label: as0_srts_reg4 reset value: 0000h label bit position type description adap_srts_remote0_read_pnt 15:0 rw the cpu's read pointer to th e adaptive point/srts value buffer. table 268 - adaptive point/srts read pointer 0 register address: 918h label: as0_srts_reg5 reset value: 0000h label bit position type description srts_local0_write_pnt 15:0 ro the chip's write pointer to the local srts value buffer. table 269 - local srts write pointer 0 register
mt90503 data sheet 196 zarlink semiconductor inc. address: 91ah label: as0_srts_reg6 reset value: 0000h label bit position type description srts_local0_read_pnt 15:0 rw the cpu's read pointer to the local srts value buffer. table 270 - local srts read pointer 0 register address: 91ch label: as1_srts_reg0 reset value: 0000h label bit position type description adap_srts1_size 15:0 rw size of the adaptive point/srts value buffer minus one. 0 means 1; ffffh means 10000h. table 271 - adaptive point/srts value 1 register address: 91eh label: as1_srts_reg1 reset value: 0000h label bit position type description adap_srts1_base_add_15_0 15:0 rw the base address of the adaptive point/srts value buffer (in points or srts values). note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. table 272 - adaptive point/srts base address low 1 register address: 920h label: as1_srts_reg2 reset value: 0000h label bit position type description adap_srts1_base_add_18_16 2:0 rw the base address of the adaptive point/srts value buffer (in points or srts values). note that since adaptive points are 8 words, bits 18:16 of the base address are ignored. reserved 15:3 rw reserved. must always be "0000_0000_0000_0" table 273 - adaptive point/srts base address high 1 register
mt90503 data sheet 197 zarlink semiconductor inc. address: 922h label: as1_srts_reg3 reset value: 0000h label bit position type description adap_srts_remote1_write_pnt 15:0 ro the chip's write pointer to the adaptive point/srts value buffer. table 274 - adaptive point/srts write pointer 1 register address: 924h label: as1_srts_reg4 reset value: 0000h label bit position type description adap_srts_remote1_read_pnt 15:0 rw the cpu's read pointer to the adaptive point/srts value buffer. table 275 - adaptive point/srts read pointer 1 register address: 926h label: as1_srts_reg5 reset value: 0000h label bit position type description srts_local1_write_pnt 15:0 ro the chip's write pointer to the local srts value buffer. table 276 - local srts write pointer 1 register address: 928h label: as1_srts_reg6 reset value: 0000h label bit position type description srts_local1_read_pnt 15:0 rw the cpu's read pointer to the local srts value buffer. table 277 - local srts read pointer 1 register
mt90503 data sheet 198 zarlink semiconductor inc. address: 92ah label: cas_reg0 reset value: 0000h label bit position type description cas_size 15:0 rw size of the cas change buffer minus 1. 0 means 1; ffffh means 10000h. table 278 - cas change buffer size register address: 92ch label: cas_reg1 reset value: 0000h label bit position type description cas_base_add_15_0 15:0 rw base address of the cas change buffer. table 279 - cas change buffer base address low register address: 92eh label: cas_reg2 reset value: 0000h label bit position type description cas_base_add_18_16 2:0 rw base address of the cas change buffer. reserved 15:3 rw reserved. must always be "0000_0000_0000_0" table 280 - cas change buffer base address high register address: 930h label: cas_reg3 reset value: 0000h label bit position type description cas_write_pnt 15:0 ro the chip's write pointer to the cas change buffer. table 281 - cas write pointer register
mt90503 data sheet 199 zarlink semiconductor inc. address: 932h label: cas_reg4 reset value: 0000h label bit position type description cas_read_pnt 15:0 rw the cpu's read pointer to the cas change buffer. table 282 - cas read pointer register address: 944h label: cas_timeout_hig reset value: 0000h label bit position type description cas_timeout_period[19:16] 3:0 rw time, in us, that a cas change report can wait in the fifo before an alarm is generated. reserved 15:4 rw reserved. must always be "0000_0000_0000" table 283 - cas timeout high register address: 946h label: cas_timeout_low reset value: 0000h label bit position type description cas_timeout_period[15:0] 15:0 rw time, in us, that a cas change report can wait in the fifo before an alarm is generated. table 284 - cas timeout low register address: 948h label: treated pulses reset value: 0000h label bit position type description cas_treated_pulse 0 pul written to '1' to indicate that cas change fifo has been treated. another alarm will not be generated until the above timeout has elapsed. reserved 15:1 pul reserved. always read as "0000_0000_0000_000" table 285 - treated pulses register
mt90503 data sheet 200 zarlink semiconductor inc. 5.5.10 h.100 registers address: a00h label: control0 reset value: 0000h label bit position type description h100_pll_ref_fallback 0 rw '0' = always use selected ex ternal clk (selected by h100_pll_ext_source) to source pll's ref input. '1' = if selected clock fails, fallback on local 16.384mhz clock. h100_pll_ext_source 1 rw '0' = source ct_c8_a_in. '1' = source ct_c8_b_in h100_pll_local_source 2 rw '0' = source pll's ref input with local 16.384mhz clock, '1' = source with selected exte rnal clk (selected via h100_pll_ext_source). h100_pll_override 3 rw '0' = use embedded pll to generate outgoing clocks. '1' = bypass pll and use local 16.384 mhz clock instead. h100_clk_loopback 4 rw '1' = loops the ct_c8 a and b clocks and frames back into the chip. used for tests h100_sclk_speed 6:5 rw "00" = 2.048 mhz. "01" = 4.096 mhz. "10" = 8.192 mhz. h100_c8_frame_a_oe 7 rw '0' = tri-states ct_c8_a and ct_frame_a h100_c8_frame_b_oe 8 rw '0' = tri-states ct_c8_b and ct_frame_b h100_comp_oe 9 rw '0' = tri-states all t he compatibility signals h100_pll_fb_input 11:10 rw selects pll's fb input: "00" = sample a, "10" = sample b, "01" = sample pll output (div 4), "11" = reserved. h100_frame_sync_sourc e 12 rw '0' = sync frame on ct_frame_a_in, '1' = sync frame on ct_frame_b_in h100_tdmint_clk_sel 13 rw specifies which clk to send to tdmint: '0' = use ct_c8_a. '1' = use ct_c8_b. h100_tdmint_clk_fallback can send other clk instead. h100_tdmint_clk_fallbac k 14 rw clk to tdmint if selected clk is bad: '0' = always sync on selected clk (h100_tdming_clk_sel). '1' = if selected clk fails, switch over to backup clk. test_status 15 ts when '1', all the status bits in the register will be set. table 286 - h.100 control 0 register
mt90503 data sheet 201 zarlink semiconductor inc. address: a02h label: control1 reset value: 0000h label bit position type description h100_force_frame_sync_local 0 rw only applies if h100_pll_override is '0': '0' = sync frame on selected external frame (h100_frame_sync_source), '1' = sync frame on local 16.384 mhz clk. reserved 15:1 rw reserved. must always be "0000_0000_0000_000" table 287 - h.100 control 1 register address: a04h label: control2 reset value: 0000h label bit position type description h100_min_mclk_ct_c8 3:0 rw minimum number of mclk cycl es between ct_c8 rising edges, typically set using this equation: ((122 - 35) / mclk_period_ns) - 2. h100_max_mclk_ct_c8 8:4 rw maximum number of mclk cycles between ct_c8 rising edges, typically set using this equation: ((122 + 35) / mclk_period_ns) + 2. reserved 15:9 rw reserved. must always be "0000_000" table 288 - h.100 control 2 register address: a08h label: flags reset value: 0000h label bit position type description h100_clk_a_bad_latched 0 ro indicates that the ct_c8_a peri od is not within +/- 35 ns of what is was supposed to be. this is a ro signal, so it means that the error is currently occurring. h100_clk_b_bad_latched 1 ro indicates that the ct_c8_b peri od is not within +/- 35 ns of what is was supposed to be. this is a ro signal, so it means that the error is currently occurring. table 289 - h.100 flags register
mt90503 data sheet 202 zarlink semiconductor inc. h100_frame_a_bad_latched 2 ro indicates that the ct_frame_a is not occurring every 1024 ct_c8_a cycles. this is a ro signal, so it means that the error is currently occurring. h100_frame_b_bad_latched 3 ro indicates that the ct_frame_b is not occurring every 1024 ct_c8_a cycles. this is a ro signal, so it means that the error is currently occurring. reserved 15:4 ro reserved. always read as "0000_0000_0000" address: a0ah label: status reset value: 0000h label bit position type description h100_clk_a_bad_rol 0 rolo indicates that the ct_c 8_a period is not within +/- 35 ns of what is was supposed to be. this is a rol signal, so it means that the error has occurred since the last time this bit was cleared. h100_clk_b_bad_rol 1 rolo indicates that the ct_c 8_b period is not within +/- 35 ns of what is was supposed to be. this is a rol signal, so it means that the error has occurred since the last time this bit was cleared. h100_frame_a_bad_rol 2 rolo indicates that the ct_frame_a is not occurring every 1024 ct_c8_a cycles. this is a rol sign al, so it means that the error has occurred since the last time this bit was cleared. h100_frame_b_bad_rol 3 rolo indicates that the ct_frame_b is not occurring every 1024 ct_c8_a cycles. this is a rol sign al, so it means that the error has occurred since the last time this bit was cleared. reserved 15:4 rolo reserved. always read as "0000_0000_0000" table 290 - h.100 status register address: a08h label: flags reset value: 0000h label bit position type description table 289 - h.100 flags register (continued)
mt90503 data sheet 203 zarlink semiconductor inc. 6.0 statistics 6.1 tdm statistics underrun counter: 16-bit c ounter that counts the number of underruns detected by tdm interface. 6.2 tx sar statistics percentage of bandwidth utilisation: a register (0510h) whic h indicates how many mclk c ycles were required to treat the last frame. transmitted cell counter: 32-bit counter that counts the number of cells tran smitted on a particular vc. each vc has its own counter in its structure. 6.3 rx sar statistics error reporting structures allow software-based counters for the following errors: ? p-byte absent error ? p-byte framing error ? p-byte range error ? p-byte parity error ? overrun error ? underrun error ? aal1 crc error ? aal1 parity error ? single cell loss ? multiple cell loss ? cell misinsertion address: a0ch label: status_ie reset value: 0000h label bit position type description h100_clk_a_bad_rol 0 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. h100_clk_b_bad_rol 1 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. h100_frame_a_bad_rol 2 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. h100_frame_b_bad_rol 3 ie when '1' and the corresponding status bit is '1', an interrupt will be generated. reserved 15:4 ie reserved. always read as "0000_0000_0000" table 291 - h.100 interrupt enable register
mt90503 data sheet 204 zarlink semiconductor inc. received cell counter: 32-bit counter that counts the num ber of cells received on a particular vc. each vc has its own counter in its structure. 6.4 utopia statistics transmitted cell counters: 32-bit counters that counts th e number of cells transmitted on a particular utopia port. three counters are available for each ports. received cell counters: 32-bit counters that counts the num ber of cells received on a particular utopia port. each port has a dedicated counter. cell loss counter: 16-bit counters that counts the number of cells lost in the utopia module. 7.0 programming the fast_clk pll the frequency received on mclk_src pin is used by the mt90503?s pll to generate a much higher frequency (fast_clk). it is then divided down to the output mem_clk frequency. the x, y and z divider can be programmed to be any value as defined in table 292 and table 293 on page 206. the mt90503 can support mclk_src with a frequency ranging from 30 mhz to 80 mhz. only frequencies between 50 mhz and 53.3 mhz are not supported by the pll. the x and y divisor indicate what values can be programmed in the pll_conf registers 128h. table 293 , ?z divisor table,? on page 206 indica tes the range of output mem_clk that can be achieved. note that the output mem_clk cannot be programmed to be above 80 mhz, or below 40 mhz. the fast_clk pll drives the output mem_clk pins. these pins provide both ttl and pecl interfaces for the output mem_clk. for both types, the output pins for the mem_clk is always driven. however, when the output pins are not being used, the register bits that control the toggli ng of these two pins should be disabled to reduce power consumption. the user must configure the mt90503 to select the desired input mem_clk type, i.e., ei ther pecl or ttl. the input mem_clk serves as the main clock (mclk) for the mt90503 and must be present for the mt90503 to function. it is absolutely necessary for the input mem_clk to be pr esent and one of the inputs to be selected. the output mem_clk, however, are convenience for the user and do not have to be connected. these outputs eliminate the need for a second, high -speed oscillator to drive the input mem_clk. the clock that is connected to the mem_clk inputs on the mt90503, whether it is the ttl or pecl, must be in phase with the clock connected to ssram used with the chip. the maximum skew allowed is 0.5 ns.
mt90503 data sheet 205 zarlink semiconductor inc. figure 50 - mem_clk output and fast_clk generation circuits figure 51 - mem_clk input and mclk generation circuit clock multiplication pll fb ref out divide by y divide by x divide by z upclk fast_clk mem_clk_o 50 ohm controled impedance output buffer (3.3 v lvttl) mem_clk_positive_o pecl output buffer mem_clk_negative_o _p _ mclk_src mem_clk_i 3.3 v lvttl input mem_clk_positive_i pecl input buffer mem_clk_negative_i + - mclk distribution buffer mclk
mt90503 data sheet 206 zarlink semiconductor inc. div x div y mclk_src (mhz) fast_clk (mhz) - - 0 to 30 - 1 6 30 to 33.33 180 to 200 1 5 33.33 to 40 166.66 to 200 1 4 40 to 50 160 to 200 - - 50 to 53.33 - 1 3 53.33 to 66.66 160 to 200 2 5 66.66 to 80 166.66 to 200 1 2 80 160 to 200 table 292 - register 0128h frequency values div z output mem_clk 280 3 53.3 to 66.6 4 40 to 50 table 293 - z divisor table
mt90503 data sheet 207 zarlink semiconductor inc. 8.0 electrical specifications 8.1 dc characteristics * exceeding these figures may cause permanent damage. functional operation under these conditions is not guaranteed. voltage measurements are with respect to ground (v ss ) unless otherwise stated. long-term exposure to absolute maximum ratings may affect device reliability, and permanent damage may o ccur if operate exceeding the rating . the device should be operated un der recommended operating condition. note 1: suitable heat sinks: part number 66435, avvid thermalloy and part number hs2141, intricast, or other similar heat sinks . typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. voltage measurements are with respect to ground (v ss ) unless otherwise stated. absolute maximum ratings parameter symbol min. max. units 1 supply voltage ? 3.3 volt rail v dd -0.3 3.9 v 2 voltage on 3.3v input pins v i -1.0 3.6 v 3 continuous current at digital inputs i i 4.0 ma 4 continuous current at digital outputs i o 5.3 ma 5 storage temperature t s -40.0 +85.0 c recommended operating conditions characteristics symbol min. ty p. max. units test conditions 1 operating temperature t op -40.0 25.0 +85.0 c 2048 channels with heat sink note 1. 2 operating temperature t op -40.0 25.0 +70.0 c 2048 channels with no heat sink 3 operating temperature t op -40.0 25.0 +85.0 c 1024 channels with no heat sink 4 supply voltage, 3.3 volt rail v dd 3.0 3.3 3.6 v 5 input voltage - 3.3 v inputs v i vss-0.5 3.3 vdd+0.3 v
mt90503 data sheet 208 zarlink semiconductor inc. dc characteristics characteristics symbol min. typ. max. units test conditions 1 supply current - 3.3 v supply i dd 720.0 ma 50.0 mhz, nominal output loads, 1024 channels, 16 streams active. 2 supply current - 3.3 v supply i ddn 970.0 ma 80.0 mhz, nominal output loads, 2048 channels 3 device power dissipation p dd1 2.38 w 50.0 mhz, nominal output loads, 1024 channels, 16 streams active. 4 device power dissipation p dd2 3.2 w 80.0 mhz, nominal output loads, 2048 channels 5 input high voltage v ih 2.0 vdd+0 .3 v 6 input low voltage v il vss-0.5 0.8 v 7 switching threshold v tc 1.4 2.0 v 8 schmitt trigger positive threshold v t+ 1.7 2.0 v 9 schmitt trigger neg. threshold v t- 0.8 1.0 v 10 input leakage current i i -10.0 10.0 av in = v ddx or v ss 11 input pin capacitance c i 2.5 pf 12 output pin capacitance c o 2.0 pf 13 output high impedance leakage i oz -10.0 +/- 1.0 10.0 av o = v ss or v dd 14 output high voltage v oh 2.4 vdd v i oh = rated current 15 output low voltage v ol 0.2 0.4 v i ol = rated current 16 3.3v output high current (4 ma buffer) i oh 4.0 ma v oh = 2.4 v 17 3.3v output low current (4 ma buffer) i ol 4.0 ma v ol = 0.4 v 18 3.3v output high current (8 ma buffer) i oh 8.0 ma v oh = 2.4 v 19 3.3v output low current (8 ma buffer) i ol 8.0 ma v ol = 0.4 v 20 3.3v output high current (12 ma buffer) i oh 12.0 ma v oh = 2.4 v
mt90503 data sheet 209 zarlink semiconductor inc. 8.1.1 precautions during power sequencing latch-up is not a concern during power sequencing. th e only requirement for sequencing 3.3 v and 5 v supplies during power up is that the mt90503 be eit her held in reset until the rails are stable or have its global_tri_state pin held low (tristate). however, to minimise over-voltage stre ss during system start-up, the 3.3 v supply applied to the mt90503 should be brought to a level of at least v dd = 3.0 v before a signal line is driven to a level greater than or equal to 3.3 v. this practice can be implemented either by ensuring that the 3.3 v power turns on simultaneously with or before the system 5 v supply turns on, or by ens uring that all 5 v signals ar e held to a logic low state during the time that v dd < 3.0 v. this condition is also met also if the mt90503 is held in reset until v dd reaches 3.0 v. regardless of the method chosen to limit over-voltage st ress during power up, exposure must be limited to no more than + 6.5 v input voltage (v in ). the global_tri_state pin of the mt90503 can be asserted low on power-up to prevent bus contention. 8.1.2 precautions during power failure latch-up is not a concern in power failure mode. alth ough extended exposure of the mt90503 to 5 v signals during 3.3 v supply power failure is not recommended, there are no restrictions as long as v in does not exceed the absolute maximum rating of 6.5 v. to minimise over-vol tage stress during a 3.3 v powe r supply failure, the designer should either link the power supplies to prevent this condition or ensure t hat all 5 v signals connected to the mt90503 are held in a logic low stat e until the 5 v supply is deactivated. 8.1.3 pull-ups pull-ups from the 5 v rail to 3.3 v (5 v tolerant) outputs of the mt90503 can cause reverse leakage currents into those 3.3v outputs when they are active high. (no significant reverse current is present during the high impedance state.) if the application can put the mt90503 in a state where mclk is stopped, and a large number of 3.3 v output buffers are held in a static high state, current can flow from the 5 v rail to the 3.3 v rail. if this mclk-stopped state can not be avoided, th e user should determine if the total mt90503 reverse current will have a negative impact on the system 3.3 v power supply. alternat ively, the global_tri_state pin of the mt90503 can be asserted low to put all outputs in the high impedance state. 8.2 h.110 diode clamp rail as the mt90503 has a diode clamp to the 5 v rail, the diode clamp must be no more than 0.7 v below v dd when the pin is not tristated. this can be accomplished by as serting the global_tri_state pin low or by keeping the mt90503 in reset until all rails are stable. 21 3.3v output low current (12 ma buffer) i ol 12.0 ma v ol = 0.4 v 22 junction-to-ambient thermal resistance j-a 14.225 c/w 0 cfm air flow (natural convection airflow only) b. t op = 0 c to 70 c; v dd = 3.3v 5% voltage measurements are with respect to ground (v ss ) unless otherwise stated. dc characteristics (continued)
mt90503 data sheet 210 zarlink semiconductor inc. 8.3 ac characteristics all pins are tested with 50 pf worst case loading and 15 pf best case loading unless otherwise specified. clock name minimum frequency maximum frequency required for device operation minimum duty cycle maximum duty cycle mem_clk_i 40 mhz 80 mhz yes 40% 60% mclk_src 30 mhz 80 mhz yes 40% 60% rxa_clk 1 mhz 50 mhz no 40% 60% rxb_clk 1 mhz 50 mhz no 40% 60% rxc_clk 1 mhz 50 mhz no 40% 60% txa_clk 1 mhz 50 mhz no 40% 60% txb_clk 1 mhz 50 mhz no 40% 60% txc_clk 1 mhz 50 mhz no 40% 60% pll_clk 8.192 mhz 65.536 mhz no 40% 60% ct_c8_a/b 8.192 mhz 8.192 mhz no 40% 60% recov_a 0 mhz 80 mhz no 40% 60% recov_b 0 mhz 80 mhz no 40% 60% recov_c 0 mhz 80 mhz no 40% 60% recov_d 0 mhz 80 mhz no 40% 60% recov_e 0 mhz 80 mhz no 40% 60% recov_f 0 mhz 80 mhz no 40% 60% recov_g 0 mhz 80 mhz no 40% 60% recov_h 0 mhz 80 mhz no 40% 60% table 294 - clock networks characteristic sym min typ max unit s test conditions mem_clk_i frequency t mf 40.0 80.0 80.0 mhz 30ppm clock recommended for tdm plls mem_clk_i pulse width (high / low) t mh/l 5.0 6.25 7.5 ns for 80mhz operation. table 295 - mclk - master clock input parameters
mt90503 data sheet 211 zarlink semiconductor inc. 9.0 interface timing 9.1 cpu interface timing figure 52 - non-multiplexed cpu write access - intel mode figure 53 - non-multiplexed cpu read access - intel mode write_active inmo_a[14:0] /inmo_das inmo_d[15:0] a ddress valid inmo_rdy data valid t1 t2 t3 t1 t3 t4 t5 t6 note : write_active = (inmo_cs = 0) and (inmo_wr = 0) inmo_a[14:0] /inmo_das inmo_d[15:0] a ddress valid inmo_rdy data valid t1 t2 t3 t8 t4 t5 t6 t7 note : read_active = (inmo_cs = 0) and (inmo_rd = 0) read_active
mt90503 data sheet 212 zarlink semiconductor inc. figure 54 - multiplexed cpu write access - intel mode symbol description write access min. typ. max. unit t1 write_access_active falling to inmo_d/inmo_a_das/inmo_a valid 2*mclk_src - 4 ns t2 inmo_rdy_ndtack rising to write_access_active rising 0 ns t3 inmo_rdy_ndtack rising to inmo_d/inmo_a_das/inmo_a invalid 0ns t4 write_access_active falling to inmo_rdy_ndtack falling 012ns t5 write access time 740 ns t6 write_access_active rising to inmo_rdy_ndtack tri-state 010ns symbol description read access min. typ. max. unit t1 read_access_active falli ng to inmo_ a_das/inmo_a valid 2*mclk_src - 4 ns t2 inmo_rdy_ndtack rising to read_access_active rising 0 ns t3 inmo_rdy_ndtack rising to inmo_a_das/inmo_a invalid 0ns t4 read_access_active falli ng to inmo_rdy_ndtack falling 012ns t5 read access time see table 300 ns t6 read_access_active rising to inmo_rdy_ndtack tri-state 010ns t7 inmo_d valid to inmo_rdy_ndtack rising mclk_src - 4 ns t8 read_access_active falling to inmo_d driving 3*mclk_src - 4 ns table 296 - non-multiplexed cpu interface intel mode inmo_d[15:0] inmo_ale address valid inmo_rdy data valid t3 t2 t4 t5 t6 t7 t8 t10 t9 note : write_active = (inmo_cs = 0) and (inmo_wr = 0) write_active t1
mt90503 data sheet 213 zarlink semiconductor inc. figure 55 - multiplexed cpu read access - intel mode symbol description write access min. typ. max. unit t1 write_access_active falling to inmo_ale falling 2*mclk_src - 4 ns t2 write_access_active falling to inmo_d valid (writes) 2*mclk_src - 4 ns t3 inmo_rdy_ndtack rising to write_access_active rising 0ns t4 inmo_rdy_ndtack rising to inmo_ale rising & inmo_d invalid 0ns t5 write access time 740 ns t6 write_access_active rising to inmo_rdy_ndtack tri-state 010ns t7 write_access_active falling to inmo_rdy_ndtack falling 012ns t8 inmo_ale high pulse width 5 ns t9 inmo_d valid to inmo_ale falling 5 ns t10 inmo_ale falling to inmo_d invalid 0 ns symbol description read access min. typ. max. unit t1 read_access_activ e falling to inmo_ale falling 2*mclk_src - 4 ns t2 inmo_rdy_ndtack rising to read_access_active rising 0ns t3 inmo_rdy_ndtack rising to inmo_ale rising 0 ns t4 read_access_active falli ng to inmo_rdy_ndtack falling 012ns t5 read access time see table 300 ns table 297 - multiplexed cpu interface intel mode inmo_d[15:0] inmo_ale address valid inmo_rdy data valid t2 t3 t5 t6 t4 t7 t11 t10 t9 note : read_active = (inmo_cs = 0) and (inmo_rd = 0) t8 read_active t1
mt90503 data sheet 214 zarlink semiconductor inc. figure 56 - non-multiplexed cpu interface write access - motorola mode t6 read_access_active rising to inmo_rdy_ndtack tri-state 010ns t7 inmo_ale high pulse width 5 ns t8 read_access_act ive falling to inmo_d driving 3*mclk_src - 4 ns t9 inmo_d valid to inmo_rdy_n dtack falling mclk_src - 4 ns t10 inmo_d valid to inmo_ale falling 5 ns t11 inmo_ale falling to inmo_d invalid 0 ns table 297 - multiplexed cpu interface intel mode (continued)
mt90503 data sheet 215 zarlink semiconductor inc. figure 57 - non-multiplexed cpu interface read access - motorola mode symbol description write access min. typ. max. unit t1 address & data setup -- inmo_cs and inmo_rd_ds asserted to inmo_a[14:0] and inmo_d[15:0] and inmo_a_das valid 2*mclk_src - 4 ns t3 address & data hold -- inmo_rdy_ndtack low to inmo_a[14:0[ and inmo_d[15:0] and inmo_a_das invalid 0ns t4 inmo_rdy_ndtack high -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack driving one 012ns t5 inmo_rdy_ndtack delay -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack driving zero 740 ns t6 inmo_rdy_ndtack hold -- inmo_cs and inmo_rd_ds de-asserted to inmo_rdy_ndtack drivingb one 010ns t7 inmo_rdy_ndtack high impedance -- inmo_rdy_ndtack driving one to inmo_rdy_ndtack high impedance 28ns t11 r/w setup -- r/w asserted to inmo_cs asserted 0 ns t12 r/w hold -- inmo_cs deasserted to r/w deasserted 0 ns note: t1, t4, and t5 are dependent upon the last of inmo_cs and inmo_rd_ds to be asserted. t6 is dependent on the first of inmo_cs and inmo_rd_ds to be de-asserted. symbol description read access min. typ. max. unit t1 address setup -- inmo_cs and inmo_rd_ds asserted to inmo_a[14:0[ and inmo_a_das valid 2*mclk_src - 4 ns table 298 - non-multiplexed cpu interface motorola mode
mt90503 data sheet 216 zarlink semiconductor inc. figure 58 - multiplexed cpu interface write access - motorola mode t3 address hold -- inmo_rdy_ndtack low to inmo_a[14:0] and inmo_a_das invalid 0ns t4 inmo_rdy_ndtack high -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack driving one 012ns t5 inmo_rdy_ndtack delay -- inmo_cs and inmo_rd_ds asserted to inmo_rdy_ndtack asserted see table 300 ns t6 inmo_rdy_ndtack hold -- inmo_cs or inmo_rd_ds de-asserted to inmo_rdy_ndtack driving one 010ns t7 inmo_rdy_ndtack high impedance -- inmo_rdy_ndtack driving one to inmo_rdy_ndtack high-impedance 28ns t9 data to inmo_rdy_ndtack delay -- inmo_d[15:0] valid to inmo_rdy_ndtack asserted mclk_src - 4 ns t10 data output hold -- inmo_cs or inmo_rd_ds de-asserted to inmo_d[15:0] invalid 010ns t11 r/w setup -- r/w asserted to inmo_cs asserted 0 ns t12 r/w hold -- inmo_cs deasserted to r/w deasserted 0 ns note: t1, t4, and t5 are dependent upon the last of inmo_cs and inmo_rd_ds to be asserted. t6, and t10 are dependent on the first of inmo_cs and inmo_rd_ds to be de-asserted. symbol description write access min. typ. max. unit table 298 - non-multiplexed cpu interface motorola mode (continued) write_active inmo_d[15:0] inmo_ale address valid inmo_rdy data valid t1 t3 t2 t4 t5 t6 t9 t8 t11 t10 notes : write_active = (inmo_cs = 0) and (inmo_ds = 0) and (inmo_r/w = 0) t7
mt90503 data sheet 217 zarlink semiconductor inc. figure 59 - multiplexed cpu interface read access - motorola mode symbol description write access min. typ. max. unit t1 write_access_active falling to inmo_ale falling 2*mclk_src - 4 ns t2 write_access_active falling to inmo_d valid (writes) 2*mclk_src - 4 ns t3 inmo_rdy_ndtack falling to write_access_active rising 0ns t4 inmo_rdy_ndtack falling to inmo_ale rising & inmo_d invalid 0ns t5 write access time 740 ns t6 write_access_active rising to inmo_rdy_ndtack rising 010ns t7 inmo_rdy_ndtack rising to inmo_rdy_ndtack tri-state 28ns t8 inmo_ale high pulse width 5 ns t9 write_access_active falling to inmo_rdy_ndtack driven high 012ns t10 inmo_d valid to inmo_ale falling 5 ns t11 inmo_ale falling to inmo_d invalid 0 ns symbol description read access min typ max unit t1 read_access_activ e falling to inmo_ale falling 2*mclk_src - 4 ns t2 inmo_rdy_ndtack falling to read_access_active rising 0ns t3 inmo_rdy_ndtack falling to inmo_ale rising 0 ns t4 read_access_active falli ng to inmo_rdy_ndtack driving high 012ns table 299 - multiplexed cpu interface motorola mode notes : read_active = (inmo_cs = 0) and (inmo_ds = 0) and (inmo_r/w = 1) read_active inmo_d[15:0] inmo_ale address valid inmo_rdy data valid t1 t2 t5 t6 t4 t11 t13 t12 t7 t8 t3 t9 t10
mt90503 data sheet 218 zarlink semiconductor inc. t5 read access time see table 300 ns t6 read_access_active rising to inmo_rdy_ndtack rising 010ns t7 inmo_rdy_ndtack rising to inmo_rdy_ndtack tri-state 28ns t8 read_access_act ive falling to inmo_d driving 3*mclk_src - 4 ns t9 inmo_d valid to inmo_rdy_n dtack falling mclk_src - 4 ns t10 read_access_active rising to inmo_d tri-state 0 10 ns t11 inmo_ale high pulse width 5 ns t12 inmo_d valid to inmo_ale falling 5 ns t13 inmo_ale falling to inmo_d invalid 0 ns symbol description burst length max. unit t5 register and internal memory access 1 word 740 ns t5 ssram 1 word 1.07 s t5 ssram 8 words 1.44 s t5 ssram 128 words 8.78 s table 300 - t5 read access time symbol description write access min. typ. max. unit table 299 - multiplexed cpu interface motorola mode (continued)
mt90503 data sheet 219 zarlink semiconductor inc. 9.2 utopia interface timing figure 60 - utopia timing characteristics symbol min. max. units 1 input setup time t1 4 ns 2 input hold time t2 1 ns 3 clock to data valid t3 12 ns 4 clock to data change t4 2 ns 5 clock rising to signal driven t5 1 ns 6 clock rising to signal tri-state t6 1 20 ns table 301 - utopia bus timing {tx,rx}{a,b,c}_clk inputs * outputs ** t5 t3 t4 t6 t1 t2 atm mode: * includes signals: {tx,rx}{a,b,c}_clav, rx{a,b,c}_soc, rx{a,b,c}_d[], rx{a,b,c}_par ** includes signals: {tx,rx}{a,b,c}_enb, tx{a,b,c}_soc, tx{a,b,c}_d[ ], tx{a,b,c}_par phy mode: * includes signals: {tx,rx}{a,b,c}_enb, rx{a,b,c}_so c, rx{a,b,c}_d[], rx{a,b ,c}_par, {tx,rx}a_addr[ ] ** includes signals: {tx,rx}{a,b,c}_clav, tx {a,b,c}_soc, tx{a,b,c}_ d[ ], tx{a,b,c}_par
mt90503 data sheet 220 zarlink semiconductor inc. 9.3 external memory timing figure 61 - flowthrough zbt external memory timing - write access figure 62 - flowthrough zbt external memory timing - read access 0ns 10ns 20ns 30ns 40ns 5 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" "00" "11" "00" data valid data valid parity valid t4 t5 t3 t4 t6 t3 t3 t4 t3 t4 t3 t4 t5 t3 t6 t4 0ns 10ns 20ns 30ns 40ns 5 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" data valid parity valid t4 t3 t3 t4 t1 t2 t6 t1 t2 t6
mt90503 data sheet 221 zarlink semiconductor inc. figure 63 - flowthrough ssram external memory timing - write access figure 64 - flowthrough ssram external memory timing - read access 0ns 10ns 20ns 30ns 4 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" "00" "11" "00" data valid data valid parity valid t4 t5 t3 t4 t6 t3 t3 t4 t3 t4 t3 t4 t5 t3 t6 t4 0ns 10ns 20ns 30ns 40ns 5 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" data valid parity valid t4 t3 t3 t4 t1 t2 t6 t1 t2 t6
mt90503 data sheet 222 zarlink semiconductor inc. figure 65 - late-write external memory timing - write access figure 66 - late-write external memory timing - read access 0ns 10ns 20ns 30ns 40ns 5 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" "00" "11" "00" data valid data valid parity valid t4 t5 t3 t4 t6 t3 t3 t4 t3 t4 t3 t4 t5 t3 t6 t4 0ns 10ns 20ns 30ns 40ns 50ns 6 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" data valid parity valid t4 t3 t3 t4 t1 t2 t6 t1 t2 t6
mt90503 data sheet 223 zarlink semiconductor inc. figure 67 - pipelined zbt external memory timing - write access figure 68 - pipelined zbt external memory timing - read access 0ns 10ns 20ns 30ns 40ns 50ns 6 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" "00" "11" "00" data valid data valid parity valid t4 t5 t3 t4 t6 t3 t3 t4 t3 t4 t3 t4 t5 t3 t6 t4 0ns 10ns 20ns 30ns 40ns 50ns 6 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" data valid parity valid t4 t3 t3 t4 t1 t2 t6 t1 t2 t6
mt90503 data sheet 224 zarlink semiconductor inc. figure 69 - pipelined external memory timing - write access figure 70 - pipelined external memory timing - read access 0ns 10ns 20ns 30ns 4 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" "00" "11" "00" data valid data valid parity valid t4 t5 t3 t4 t6 t3 t3 t4 t3 t4 t3 t4 t5 t3 t6 t4 0ns 10ns 20ns 30ns 40ns 50ns 6 mem_clk mem_cs mem_rw mem_a mem_bws mem_d mem_par address valid address valid "11" data valid parity valid t4 t3 t3 t4 t1 t2 t6 t1 t2 t6
mt90503 data sheet 225 zarlink semiconductor inc. 9.4 h.100/h.110 interface timing figure 71 - h.100 input, output, and frame sampling characteristics symb ol min. typ. max. units test conditions 1 input setup time t1 2 ns 2 input hold time t2 0 ns 3 clock to data valid t3 8.30 ns primetime tested (load = 50 pf) 4 clock to data change t4 2 ns primetime tested (load = 50 pf) 3s clock to data valid t3 7 ns spi ce tested with 2 memory chips 4s clock to data change t4 2 ns s pice tested with 2 memory chips 5 clock rising to signal driven t5 2 ns 6 clock rising to signal tri-state t6 10 ns table 302 - memory interface timing ct_c cd d ( 1/2 c y cle ) cd_d ( 3/4 c y cle ) cd d ( 4/4 c y cle ) t2 t3 t4 t5 t6 h.100 input sampling ct_c cd_d (end of time-slot; early tri-state) cd_d (middle of time-slot) h.100 cd_d (beginning of time-slot) x t1 t1 t1 t1 t1 ct_c8 ct_frame h.100 frame t2 t2 t
mt90503 data sheet 226 zarlink semiconductor inc. figure 72 - h.100 message channel clock, transmission delay, and reception delay figure 73 - h.100 clock skew (when chip is master) ct_c8 ct_frame h.100 message channel clock mc_clock t30 t31 mc _ t ct_mc h.100 message transmission delay t40 t41 ct_mc mc_rx h.100 message reception delay t50
mt90503 data sheet 227 zarlink semiconductor inc. 9.5 h.100/h.110 clocking signals the mt90503's h.100/h.110 interface generates all of the following signals with the specified timing. figure 74 - h.100/h. 110 clocking signals symbol description min. typical max. unit notes t1 ct_c8 rise to ct_d valid 69 ns t2 ct_c8 rise to ct_d invalid 102 ns t3 ct_d valid to ct_c8 fall 3 ns t4 ct_c8 fall to ct_d invalid 1 ns t5 ct_d valid to ct_c8 rise 5 ns t6 ct_c8 rise to ct_d invalid 0 ns t10 ct_c8 rise to ct_d tri-state 122 ns 200 pf t11 ct_c8 rise to ct_d invalid 102 ns 200 pf t12 ct_c8 rise to ct_d invalid 2 ns 200 pf t13 ct_c8 rise to ct_d driven 2 ns 200 pf t14 ct_c8 rise to ct_d valid 22 ns 200 pf t20 ct_frame valid to ct_c8 rise 5 ns t21 ct_c8 rise to ct_frame invalid 5 ns t30 ct_c8 rise to mc_clock rise 15 ns t31 ct_c8 fall to mc_clock fall 15 ns t40 mc_tx fall to ct_mc low 3 15 ns 200 pf t41 mc_tx rise to ct_mc tri-state 3 15 ns 200 pf t50 ct_mc fall to mc_rx fall 3 15 ns t60 ct_c8_a, ct_c8_b, ct_frame_a, ct_frame_b, c2, c4, sclk, sclkx2, frcomp, c16+, c16- maximum skew when generated by the chip 5ns200 pf table 303 - h.100/h.110 interface timing /ct_frame ct_dx time slot 125 us 878 0 123456 127 1 78 123456 ct_c8
mt90503 data sheet 228 zarlink semiconductor inc. figure 75 - tdm bus timing - compatibility clock generation c2 /c4 sclk sclkx2* sclk (2.048mhz) (2.048mhz) (4.096mhz) sclk (8.192mhz) /c16 /ct_frame(a/b) ct_c8(a/b) /fr_comp sclkx2* (4.096mhz) sclkx2* (8.192mhz)
mt90503 data sheet 229 zarlink semiconductor inc. figure 76 - tdm data bus timings symbol parameter min. typ. max. units clock edge rate (all clocks) 0.25 2 v/ns tc8p clock ct_c8 period 122.066-f 122.074+f ns tc8h clock ct_c8 high time 49-f 73+f ns tc8l clock ct_c8 low time 49-f 73+f ns tsamp data sample point 90 ns tdoz data output to hiz time -20 0 ns tzdo data hiz to output time 0 22 ns tdod data output delay time 0 22 ns tdv data valid time 0 69 ns tdiv data invalid time 102 112 ns tfp /ct_frame width 90 122 180 ns tfs /ct_frame setup time 45 90 ns tfh /ct_frame hold time 45 90 ns f phase correction 0 10 ns table 304 - h.100/h.110 clocking signals /ct_frame tfs tfh tfp 0.6v 2.0v data out data in bit 1 bit 8 1 bit cell tdv tdod tdiv tdoz ts 0 ts 127 2.4v 0.4v 1.4v ct_c8 tc8h tc8l tc8p 2.0v 0.6v tzdo tsamp
mt90503 data sheet 230 zarlink semiconductor inc. 10.0 glossary of terms aal0: a tm a daptation l ayer 0 . aal0 is a straight packaging of 48 bytes of data within an atm cell. aal0 can be used to treat either data cells (managed by cpu) or cbr cells (managed by tx/rx sar). aal1: a tm a daptation l ayer 1 . aal1 is used to transport constant bit rate (cbr) data on atm. the main features of aal1 are a cell sequence number that allows the detection of lost cells and a p-byte that allows reconverging of multi-channel vcs. aal5: a tm a daptation l ayer 5 . the main feature of aal5 is a 32-bit crc at the end of the cell that allows the detection and correction of errors in the data payload. in this design, aal5 cells are used uniquely to treat cbr information. atm: a synchronous t ransfer m ode. atm is a networking standard based on 53-byte cells and is capable of carrying voice, data and video information simultaneously. cas: c hannel a ssociated signalling . signalling bits used to indicate the state of the channel. cbr: c onstant b it r ate. cells in cbr format are sent out at a r egular rate. cbr is applicable to voice channels. cdv: c ell d elay v ariation. when cells arrive on a utopia port, they arrive with a certain delay with respect to when they were sent. cdv is a measure of how much that delay varies on a vc. clp: c ell l oss p riority. a 1-bit field in the atm cell header that corresponds to the loss priority of a cell; cells with clp = 1 can be discarded in a congestion situation. cnt : c ounter. events in the mt90503 will cause the counter to increment. crc: c yclic r edundancy c heck. the crc is a method of error detection and correction that is applied to a certain field of data. crc is an efficient me thod of error detection because the odds of erroneously detecting a correct payload are low. ds1: d igital- s ignal level 1 . ds1 is an electrical interface for digita l transmissions that contains 24 64-kbps channels. the physical interface defined to carry ds1 channels is t1. e1: e1 is the european equivalent of t1. they are simila r with the main difference being e1 runs at 2.048 mhz instead of 1.544 mbps, carrying 30 64kbps channels. esf: e xtended s uper- f rame. esf is a t1 format that defines multifra mes as consisting of 24 frames, each one of which contains 1 byte per channel. fastcas: fastcas is not an acronym. it is capitalised in this document because it is a reserved word. fastcas means that multiframe integrity is not respected between the tdm and atm buses. the tdm data is processed as soon as it is received, while cas is sent when it is available. fifo: f irst i n, f irst o ut. a fifo memory is one in which the first byte to have been written into the memory is the first one to be read from the read port. gfc: g eneric f low c ontrol. the gfc field is kept in the 4 highest bits of an atm cell?s header and is used for local functions (not carried end-to-end). the default value is "0000", meaning that gfc protocol is not enforced. gpi: g eneral p urpose i nput gpi/o: g eneral p urpose i nput or o utput h.100/h.110 : a tdm bus standard developed by ectf to provi de backward compatibility to existing tdm buses with more bandwidth and potential for development. hec: h eader e rror c heck. using the fifth octet in the atm cell header, atm equipment may check for an error and correct the contents of the header. a crc algorithm allo ws for single-error correcti on and multiple-error detection.
mt90503 data sheet 231 zarlink semiconductor inc. ie : i nterrupt e nable. this is a register bit that enables a status event to generate an interrupt. this bit is always active-high. isr: i nterrupt s ervice r outine jtag: j oint t est a ction g roup. lut: l ook- u p t able. in the utopia module of the mt90503, the lu t is used to associate the data from received cells with the proper tdm output channels. the lut is contained in the external memory. mfs : m ulti- f rame s upport. the mt90503 is capable of supporting the multi-frame standards of e1 and t1. mvip: m ulti- v endor i ntegration p rotocol. mvip is a standard for transmitting data on a tdm bus. nni: n etwork- n ode i nterface. nni atm cells do not have a gfc ni bble, instead having an extra nibble of vpi. oam: o perations a dministration and m aintenance. msb within the pti field of the atm cell header which indicates if the atm cell carries management information such as fault indications. oc-3: o ptical c arrier level- 3 . a sonet channel that carries a bandwidth of 155.55 mbps. oc-12: o ptical c arrier level- 12 . a sonet channel that carries a bandwidth of 622.08 mbps. pc : p rocess c ontrol bit. this is a register bit ty pe that is written to ?1? to initiate a hardware process. when the process completes, the hardware clears the bit. pcm: p ulse c ode m odulation. pcm is the basic method of encod ing an analog voice signal into digital form. phy: phy sical layer. the bottom layer of the atm reference model, it provides atm cell transmission over the physical interfaces that interconnect the various atm devices. pll: p hase l ock l oop. a phase lock loop is a component that generates an output clock by synchronising itself to an input clock. plls are often used to multiply the frequency of clocks. pti: p ayload t ype i dentifier. the pti field is a 3-bit header field that encodes va rious cell management information. bit 2 (msb) indicates oam information or user data, bit 1 is explicit forward congesti on control indication (whether the cell may have been delayed by network congesti on -- never examined by the mt90503) and bit 0 (lsb) indicates that a cbr-aal5 cell is the final cell in a frame. pul : pul se bit. this is a register bit that is written to ?1? to indicate an event to the hardware. this bit is always read at ?0?. ram: r andom a ccess m emory. ram is the main memory in the computer. it is called ?random? because any random address can be accessed in an equal amount of time. ro: r ead o nly. this serves to define registers that cannot be written to by the cpu. rol: r ead o nly l atch. this defines status bits. status bits cannot be written to ?1? by the cpu; however, once the status bit is set, the cpu can clear it by writing a ?0? over it. rw: r ead w rite. this type of regi ster bit will be readable and writeable by the cpu. sar: s egmentation a nd r eassembly. method of partitioning, at the source, frames into atm cells and reassembling, at the destination, these cells back into in formation frames; lower sublayer of the aal which inserts data from the information frames into cells and then a dds the required header, trailer, and/or padding bytes to create 48-byte payloads to be transmitted to the atm layer. scsa : signal computing system architecture srts: s ynchronous r esidual t ime s tamp. srts is a clock recovery techni que, which transmits timing information over the network to allow the source clock to be recons tructed at the other end. srts is sent in a 4-bit value transmitted over 8 aal1 cells.
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes: conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 40.20 39.80 35.56 ref 503 1.27 0.60 0.90 35.56 ref 1.10 39.80 min 0.50 2.11 40.20 2.56 0.70 max 6. substrate thickness is 0.56 mm ref 4. n is the number of solder balls 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 5. not to scale. note: e a a1 a2 b 3. seating plane is defined by the spherical crowns of the solder balls. e1 d1 e / 4 d / 4 d e2 d2 e dimension 1.25 d2 37.50 39.50 e2 37.50 39.50 n
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